Datasheet

MCP3911
DS22286A-page 40 © 2012 Microchip Technology Inc.
5.9 RESET Effect On Delta-Sigma
Modulator/SINC Filter
When the RESET pin is logic low, both ADCs will be in
Reset and output code 0x0000h. The RESET
pin per-
forms a hard reset (DC biases still on, part ready to
convert) and clears all charges contained in the Delta-
Sigma modulators. The comparator’s output is 0011
for each ADC.
The SINC filters are all reset, as well as their double
output buffers. This pin is independent of the serial
interface. It brings all the registers to the default state.
When RESET
is logic low, any write with the SPI
interface, will be disabled and will have no effect. All
output pins (SDO, DR, MDAT0/1) are high impedance.
If MCLK is applied, the input structure is enabled and is
properly biasing the substrate of the input transistors.
In this case, the leakage current on the analog inputs is
low, if the analog inputs are between -1V and +1V.
If MCLK is not applied, when in reset mode, the leak-
age can be high if the analog inputs are below -0.6V,
referred to AGND.
5.10 Phase Delay Block
The MCP3911 incorporates a phase delay generator,
which ensures that the two ADCs are converting the
inputs with a fixed delay between them. The two ADCs
are synchronously sampling but the averaging of
modulator outputs is delayed, so that the SINC filter
outputs (thus the ADC outputs), show a fixed phase
delay, as determined by the PHASE register’s setting.
The phase value (PHASE<11:0>) is a 11 bit + sign,
MSB first, two's complement code that indicates how
much phase delay there is to be between Channel 0
and Channel 1. The four MSB of the first phase register
(address 0x07) are undefined and set to 0. The refer-
ence channel for the delay is Channel 1 (typically the
voltage channel for power metering applications).
When PHASE<11:0> is positive, Channel 0 is lagging
versus Channel 1. When PHASE<11:0> is negative,
Channel 0 is leading versus Channel 1. The amount of
delay between two ADC conversions is shown in the
following formula.
EQUATION 5-5:
The timing resolution of the phase delay is 1/DMCLK,
or 1 µs in the default configuration with MCLK = 4 MHz.
The data ready signals are affected by the phase delay
settings. Typically, the time difference between the data
ready pulses of channel 0 and channel 1, is equal to the
phase delay setting.
5.10.1 PHASE DELAY LIMITS
The Phase delay can only go from -OSR/2 to +OSR/2 -
1. This sets the fine phase resolution. The phase
register is coded with two's complement.
If larger delays between the two channels are needed,
they can be implemented externally to the chip with an
MCU. A FIFO in the MCU can save incoming data from
the leading channel for a number N of DRCLK clocks.
In this case, DRCLK would represent the coarse timing
resolution, and DMCLK the fine timing resolution. The
total delay will then be equal to:
Delay = N/DRCLK + PHASE/DMCLK
The Phase delay register can be programmed once,
with the OSR=4096 setting, and will adjust to the OSR
automatically afterwards without the need to change
the value of the PHASE register.
•OSR=4096: the delay can go from -2048 to
+2047.PHASE<11> is the sign bit. Phase<10> is
the MSB and PHASE<0> the LSB.
•OSR=2048: the delay can go from -1024 to
+1023. PHASE<10> is the sign bit. Phase<9> is
the MSB and PHASE<0> the LSB.
•OSR=1024: the delay can go from -512 to +511.
PHASE<9> is the sign bit. Phase<8> is the MSB
and PHASE<0> the LSB.
•OSR=512: the delay can go from -256 to +255.
PHASE<8> is the sign bit. Phase<7> is the MSB
and PHASE<0> the LSB.
• OSR=256: the delay can go from -128 to +127.
PHASE<7> is the sign bit. Phase<6> is the MSB
and PHASE<0> the LSB.
• OSR=128: the delay can go from -64 to +63.
PHASE<6> is the sign bit. Phase<5> is the MSB
and PHASE<0> the LSB.
• OSR=64: the delay can go from -32 to +31.
PHASE<5> is the sign bit. Phase<4> is the MSB
and PHASE<0> the LSB.
• OSR=32: the delay can go from -16 to +15.
PHASE<4> is the sign bit. Phase<3> is the MSB
and PHASE<0> the LSB.
Delay
Phase Register Code
DMCLK
--------------------------------------------------=
Note: A detailed explanation of the data ready
pin (DR
) with phase delay is Figure 6-9.
Note: Re-writing the PHASE registers with the
same value resets and automatically
restarts both ADCs.