Datasheet

© 2012 Microchip Technology Inc. DS22286A-page 37
MCP3911
5.6 ADC Output Coding
The second order modulator, SINC
3
+SINC
1
filter, PGA,
V
REF
and analog input structure, all work together to
produce the device transfer function for the analog to
digital conversion, Equation 5-3.
The channel data is either a 16-bit or 24-bit word,
presented in 23-bit or 15-bit plus sign, two’s
complement format and is MSB (left) justified.
The ADC data is two or three bytes wide depending on
the WIDTH bit of the associated channel. The 16-bit
mode includes a round to the closest 16-bit word
(instead of truncation), in order to improve the accuracy
of the ADC data.
In case of positive saturation (CHn+ - CHn- > V
REF
/
1.5), the output is locked to 7FFFFF for 24 bit mode
(7FFF for 16 bit mode). In case of negative saturation
(CHn+ - CHn- <-V
REF
/1.5), the output code is locked to
800000 for 24-bit mode (8000 for 16 bit mode).
Equation 5-3 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC
3
+SINC
1
filter (see
Equation 5-1 and Equation 5-3).
EQUATION 5-3:
The ADC resolution is a function of the OSR
(Section 5.5 “SINC3 + SINC1 Filter”). The resolution
is the same for both channels. No matter what the res-
olution is, the ADC output data is always presented in
24-bit words, with added zeros at the end, if the OSR is
not large enough to produce 24-bit resolution (left
justification).
DATA_CHn
CH
n+
CH
n-
–()
V
REF+
V
REF-
–
-------------------------------------
⎝⎠
⎛⎞
8,388,608 G 1.5
××× =
DATA_CHn
CH
n+
CH
n-
–()
V
REF+
V
REF-
–
-------------------------------------
⎝⎠
⎛⎞
32 768,G1.5 ××× =
(For 24-bit Mode Or WIDTH = 1)
(For 16-bit Mode Or WIDTH = 0)
TABLE 5-5: OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal
Decimal, 24-bit
Resolution
0111 1111 1111 1111 1111 1111 0x7FFFFF + 8,388,607
0111 1111 1111 1111 1111 1110 0x7FFFFE + 8,388,606
0000 0000 0000 0000 0000 0000 0x000000 0
1111 1111 1111 1111 1111 1111 0xFFFFFF -1
1000 0000 0000 0000 0000 0001 0x800001 - 8,388,607
1000 0000 0000 0000 0000 0000 0x800000 - 8,388,608
TABLE 5-6: OSR = 128 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First) Hexadecimal
Decimal
23-bit Resolution
0111 1111 1111 1111 1111 111
0 0x7FFFFE + 4,194,303
0111 1111 1111 1110 1111 110
0 0x7FFFFC + 4,194,302
0000 0000 0000 0000 0000 000
0 0x000000 0
1111 1111 1111 1111 1111 1110 0xFFFFFE -1
1000 0000 0000 0000 0000 0010 0x800002 - 4,194,303
1000 0000 0000 0000 0000 000
0 0x800000 - 4,194,304