Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 24 Bit SSOP 20

MCP3911

EQUATION 5-2: SETTING TIME OF THE ADC AS A FUNCTION OF DMCLK PERIODS

The SINC

filter following the SINC

filter is only

enabled for the high OSR settings. This SINC

filter

provides additional rejection at a low cost with little

modification to the -3 dB bandwidth. For 24-Bit Output

mode (WIDTH = 1), the output of the sinc filter is pad-

ded on the right with least significant zeros, up to 24

bits, for any resolution less than 24 bits. For 16-Bit Out-

put modes, the output of the sinc filter is rounded to the

closest 16-bit number, in order to conserve only 16-bit

words and to minimize truncation error.

The gain of the transfer function of this filter is 1 at each

multiple of DMCLK (typically 1 MHz) so a proper anti-

aliasing filter must be placed at the inputs. This will

attenuate the frequency content around DMCLK and

keep the desired accuracy over the baseband of the

converter. This anti-aliasing filter can be a simple, first-

order RC network with a sufficiently low time constant

to generate high rejection at DMCLK frequency

Any unsettled data is automatically discarded to avoid

data corruption. Each data ready pulse corresponds to

fully settled data at the output of the decimation filter.

The first data available at the output of the decimation

filter is present after the complete settling time of the fil-

ter (see Table 5-4). After the first data has been pro-

cessed, the delay between two data ready pulses is 1/

DRCLK. The data stream from input to output is

delayed by an amount equal to the settling time of the

filter (which is the group delay of the filter).

The achievable resolution, the -3 dB bandwidth and the

settling time at the output of the decimation filter (the

output of the ADC), is dependent on the OSR of each

sinc filter and is summarized with the following table:

SettlingTime DMCLKPeriods()3 OSR

× OSR

1–()OSR

×+=

TABLE 5-4: OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME

OSR<2:0> OSR

OSR

TOTAL OSR RESOLUTION IN

BITS (NO MISSING

CODES)

SETTLING

TIME

-3 dB BANDWIDTH

0 0 0 32 1 32 17 96/DMCLK 0.26*DRCLK

0 0 1 64 1 64 20 192/DMCLK 0.26*DRCLK

0 1 0 128 1 128 23 384/DMCLK 0.26*DRCLK

0 1 1 256 1 256 24 768/DMCLK 0.26*DRCLK

1 0 0 512 1 512 24 1536/DMCLK 0.26*DRCLK

1 0 1 512 2 1024 24 2048/DMCLK 0.37*DRCLK

1 1 0 512 4 2048 24 3072/DMCLK 0.42*DRCLK

1 1 1 512 8 4096 24 5120/DMCLK 0.43*DRCLK