Datasheet

MCP3911
DS22286A-page 32 © 2012 Microchip Technology Inc.
modulator is still functional, however its stability is no
longer guaranteed and therefore it is not recommended
to exceed this limit (see FIGURE 2-24: “SINAD vs.
Input Signal Amplitude.” for extended dynamic range
performance limitations). The saturation point for the
modulator is V
REF
/1.5 since the transfer function of the
ADC includes a gain of 1.5 by default (independent
from the PGA setting. See Section 5.6 “ADC Output
Coding”).
5.3.3 BOOST SETTINGS
The Delta-Sigma modulators include a programmable
biasing circuit in order to further adjust the power con-
sumption to the sampling speed applied through the
MCLK. This can be programmed through the
BOOST<1:0> bits which are applied to both channels
simultaneously.
The maximum achievable analog master clock speed
(AMCLK) and the maximum sampling frequency
(DMCLK), and therefore the maximum achievable data
rate (DRCLK), highly depend on BOOST<1:0> and
PGA_CHn<2:0> settings. The following table specifies
the maximum AMCLK possible to keep optimal accu-
racy in function of BOOST<1:0> and PGA_CHn<2:0>
settings.
TABLE 5-2: MAXIMUM AMCLK LIMITS AS A FUNCTION OF BOOST AND PGA GAIN
Conditions V
DD
= 3.0V to 3.6V, T
A
from -40°C to 125°C V
DD
= 2.7V to 3.6V, T
A
from -40°C to 125°C
Boost Gain Maximum AMCLK
(MHz) (SINAD within
-3 dB from its
maximum)
Maximum AMCLK
(MHz) (SINAD
within -5 dB from its
maximum)
Maximum AMCLK
(MHz) (SINAD
within -3 dB from
its maximum)
Maximum AMCLK
(MHz) (SINAD within -
5 dB from its
maximum)
0.5x 1 3 3 3 3
0.66x 1 4 4 4 4
1x 1 10 10 10 10
2x 1 16 16 16 16
0.5x 2 2.5 3 3 3
0.66x 2 4 4 4 4
1x 2 10 10 10 10
2x 2 14.5 16 13.3 14.5
0.5x 4 2.5 2.5 2.5 2.5
0.66x 4 4 4 4 4
1x 4 10 10 8 10
2x 4 13.3 16 10.7 11.4
0.5x 8 2.5 2.5 2.5 2.5
0.66x 8 4 4 4 4
1x 8 10 11.4 6.7 8
2x 8 10 14.5 8 8
0.5x 16 2 2 2 2
0.66x 16 4 4 4 4
1x 16 10.6 10.6 8 10
2x 16 12.3 16 8 10.7
0.5x 32 2 2 2 2
0.66x 32 4 4 4 4
1x 32 10 11.4 8 10
2x 32 13.3 16 8 10