Datasheet

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MCP3911

5.0 DEVICE OVERVIEW

5.1 Analog Inputs (CHn+/-)

The MCP3911 analog inputs can be connected directly

to current and voltage transducers (such as shunts,

current transformers, or Rogowski coils). Each input

pin is protected by specialized ESD structures that are

certified to pass 4.0 kV HBM and 200V MM contact

charge. These structures allow bipolar ±2V continuous

voltage with respect to AGND, to be present at their

inputs without the risk of permanent damage.

Both channels have fully differential voltage inputs for

better noise performance. The absolute voltage at each

pin, relative to AGND, should be maintained in the ±1V

range during operation, in order to ensure the specified

ADC accuracy. The common-mode signals should be

adapted to respect both the previous conditions and

the differential input voltage range. For best

performance, the common-mode signals should be

maintained to AGND.

5.2 Programmable Gain Amplifiers

(PGA)

The two Programmable Gain Amplifiers (PGAs) reside

at the front-end of each Delta-Sigma ADC. They have

two functions: translate the common-mode of the input

from AGND to an internal level between AGND and

VDD

, and amplify the input differential signal. The

translation of the common mode does not change the

differential signal but recenters the common-mode so

that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals,

but the differential input range of the Delta-Sigma

modulator must not be exceeded. The PGA is

controlled by the PGA_CHn<2:0> bits in the GAIN reg-

ister. The following table represents the gain settings

for the PGA:

5.3 Delta-Sigma Modulator

5.3.1 ARCHITECTURE

Both ADCs are identical in the MCP3911, and they

include a proprietary second-order modulator with a

multi-bit 5-level DAC architecture (see Figure 5-1). The

quantizer is a flash ADC composed of four compara-

tors, with equally spaced thresholds, and a thermome-

ter output coding. The proprietary 5-level architecture

ensures minimum quantization noise at the outputs of

the modulators without disturbing linearity or inducing

additional distortion. The sampling frequency is

DMCLK (typically 1 MHz with MCLK=4 MHz) so the

modulator outputs are refreshed at a DMCLK rate. The

modulator outputs are available in the MOD register or

serially transferred on each MDAT pin.

Figure 5-1 represents a simplified block diagram of the

Delta-Sigma ADC present on MCP3911.

FIGURE 5-1: Simplified Delta-Sigma ADC

Block Diagram.

5.3.2 MODULATOR INPUT RANGE AND

SATURATION POINT

For a specified voltage reference value of 1.2V, the

modulators specified differential input range is

±600 mV. The input range is proportional to V

REF

and

scales according to the V

REF

voltage. This range is

guaranteeing the stability of the modulator over

amplitude and frequency. Outside of this range, the

Note: If the analog inputs are held to a potential

of -0.6 to -1V, for extended periods of time,

the clock MCLK must be present inside

the device in order to avoid large leakage

currents at the analog inputs. This is true

even during the hard reset mode or the

soft reset of both ADCs. However during

shutdown mode of the two ADCs or POR

state, the clock is not distributed inside the

circuit. During these states, it is recom-

mended to keep the analog input voltages

above -0.6V referred to AGND, to avoid

high analog inputs leakage currents.

TABLE 5-1: PGA CONFIGURATION

SETTING

Gain

PGA_CHn<2:0>

Gain

(V/V)

Gain

(dB)

Range

(V)

000 1 0±0.6

001 2 6±0.3

010 4 12±0.15

0 1 1 8 18 ±0.075

1 0 0 16 24 ±0.0375

1 0 1 32 30 ±0.01875

Note: The 2 undefined settings are G=1; this table

is defined with V

REF

= 1.2V.

Second-

Order

Integrator

Loop

Filter

Quantizer

DAC

Differential

Voltage Input

Output

Bitstream

5-level

Flash ADC

MCP3911 Delta-Sigma Modulator