Datasheet

© 2012 Microchip Technology Inc. DS22286A-page 29
MCP3911
ADC shutdown mode also effects the modulator output
block, i.e., if MDAT of the channel in shutdown mode is
enabled, this pin will provide a bitstream corresponding
to a zero output (series of 0011 bits continuously
repeated).
When an ADC exits ADC shutdown mode, any phase
delay present before shutdown was entered will still be
present. If one ADC was not in shutdown, the ADC
leaving shutdown mode will automatically
resynchronize the phase delay, relative to the other
ADC channel, per the phase delay register block and
give data ready pulses accordingly.
If an ADC is placed in shutdown mode while the other
is converting, it is not shutting down the internal clock.
When going back out of shutdown, it will be
resynchronized automatically with the clock that did not
stop during reset.
If both ADCs are ADC shutdown modes, the clock is no
more distributed to the digital core for low power oper-
ation. The clock is no more distributed to the input
structure too. This can cause potential high analog
input leakage currents at the analog inputs if the input
voltage is highly negative (typically below -0.6V,
referred to AGND).
Once any of the ADC is back to nor-
mal operation, the clock is automatically distributed
again.
4.22 Full Shutdown Mode
The lowest power consumption can be achieved when
SHUTDOWN<1:0>=11, VREFEXT=CLKEXT=1. This
mode is called “Full shutdown mode”, and no analog
circuitry is enabled. In this mode, both AV
DD
and DV
DD
POR monitoring are also disabled. No clock is propa-
gated throughout the chip. Both ADCs are in shutdown,
and the internal voltage reference is disabled.
The clock is no more distributed to the input structure
too. This can cause potential high analog inputs leak-
age currents at the analog inputs if the input voltage is
highly negative (typically below -0.6V, referred to
AGND).
The only circuit that remains active is the SPI interface
but this circuit does not induce any static power
consumption. If SCK is idle, the only current
consumption comes from the leakage currents induced
by the transistors and is less than 1 µA on each power
supply.
This mode can be used to power down the chip
completely and avoid power consumption when there
is no data to convert at the analog inputs. Any SCK or
MCLK edge coming while in this mode will induce
dynamic power consumption.
Once any of the SHUTDOWN, CLKEXT and VREFEXT
bits return to 0, the two POR monitoring blocks are
back to operation and AV
DD
and DV
DD
monitoring can
take place.
When exiting full Shutdown mode, the device resets to
its default configuration state. The Configuration bits all
reset to their default value, and the ADCs reset to their
initial state, requiring 3 DRCLK periods for an initial
data ready pulse. Exiting full Shutdown mode is effec-
tively identical to an internal reset or returning from a
POR condition.