Datasheet

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MCP3911

EQUATION 4-11:

Where V

= (CHn+ + CHn-)/2 is the common-mode

input voltage and V

OUT

is the equivalent input voltage

that the output code translates to with the ADC transfer

function. In the MCP3911 specification, VCM varies

from -1V to +1V.

4.19 ADC Reset Mode

ADC Reset mode (called also soft reset mode) can only

be entered through setting high the RESET<1:0> bits in

the configuration register. This mode is defined as the

condition where the converters are active but their

output is forced to 0.

The registers are not affected in this reset mode and

retain their except the data registers of the correspond-

ing channel which are reset to 0.

The ADCs can immediately output meaningful codes

after leaving reset mode (and after the sinc filter settling

time). This mode is both entered and exited through

setting of bits in the configuration register.

Each converter can be placed in soft reset mode

independently. The configuration registers are not

modified by the soft reset mode.

A data ready pulse will not be generated by any ADC

while in reset mode.

Reset mode also effects the modulator output block,

i.e., the MDAT pin, corresponding to the channel in

reset. If enabled, it provides a bitstream corresponding

to a zero output (a series of 0011 bits continuously

repeated).

When an ADC exits ADC reset mode, any phase delay

present before reset was entered will still be present. If

one ADC was not in reset, the ADC leaving reset mode

will resynchronize automatically the phase delay

relative to the other ADC channel per the phase delay

If an ADC is placed in Reset mode while the other is

converting, it is not shutting down the internal clock.

When going back out of reset, it will be resynchronized

automatically with the clock that did not stop during

reset.

If both ADCs are in soft reset the clock is no longer dis-

tributed to the digital core for low power operation.

Once any of the ADC is back to normal operation, the

clock is automatically distributed again.

However, when the two channels are in soft reset, the

input structure is still clocking if MCLK is applied in

order to bias properly the inputs so that no leakage cur-

rent is observed. If MCLK is not applied, large analog

input leakage currents can be observed for highly neg-

ative input voltages (typically below -0.6V referred to

AGND).

4.20 Hard Reset Mode (RESET = 0)

This mode is only available during a POR or when the

RESET

pin is pulled low. The RESET pin low state

places the device in a hard reset mode.

In this mode all internal registers are reset to their

default state.

The DC biases for the analog blocks are still active, i.e.,

the MCP3911 is ready to convert. However, this pin

clears all conversion data in the ADCs. In this mode,

the MDAT outputs are in high impedance. The

comparator’s outputs of both ADCs are forced to their

reset state (0011). The SINC filters are all reset, as well

as their double output buffers. See serial timing for

minimum pulse low time, in Section 1.0 “Electrical

Characteristics”.

During a hard reset, no communication with the part is

possible. The digital interface is maintained in a reset

state.

During this state, the clock MCLK can be applied to the

part in order to properly bias the input structures of both

channels. If not applied, large analog input leakage cur-

rents can be observed for highly negative input signals

and after removing the RESET state a certain start up

time is necessary to bias the input structure properly.

During this delay the ADC conversions can be inaccu-

rate.

4.21 ADC Shutdown Mode

ADC shutdown mode is defined as a state where the

converters and their biases are off, consuming only

leakage current. When Shutdown bit is reset to 0, the

analog biases will be enabled, as well as the clock and

the digital circuitry. The ADC will give a data ready after

the SINC filter settling time has occurred. However,

since the analog biases are not completely settled at

the beginning of the conversion, the sampling may not

be accurate during about 1 ms (corresponding to the

settling time of the biasing in worst case conditions). In

order to guarantee the accuracy, the data ready pulse,

coming within the delay of 1 ms + settling time of the

SINC filter, should be discarded.

Each converter can be placed in shutdown mode

independently. The CONFIG registers are not modified

by the shutdown mode. This mode is only available

through programming of the SHUTDOWN<1:0> bits

the CONFIG register.

The output data is flushed to all zeros while in ADC

shutdown. No data ready pulses are generated by any

ADC while in ADC shutdown mode.

CMRR dB() 20

OUT

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