Datasheet
MCP3911
DS22286A-page 26 © 2012 Microchip Technology Inc.
4.11 Total Harmonic Distortion (THD)
The total harmonic distortion is the ratio of the output
harmonics power to the fundamental signal power for a
sinewave input and is defined by the following
equation.
EQUATION 4-6:
The THD calculation includes the first 35 harmonics for
the MCP3911 specifications. The THD is usually only
measured with respect to the 10 first harmonics. THD
is sometimes expressed in %. For converting the THD
in %, here is the formula:
EQUATION 4-7:
This specification depends mainly on the DITHER set-
ting.
4.12 Spurious-Free Dynamic Range
(SFDR)
The ratio between the output power of the fundamental
and the highest spur in the frequency spectrum. The
spur frequency is not necessarily a harmonic of the
fundamental even though it is usually the case. This
figure represents the dynamic range of the ADC when
a full-scale signal is used at the input. This specification
depends mainly on the DITHER setting.
EQUATION 4-8:
4.13 MCP3911 Delta-Sigma
Architecture
The MCP3911 incorporates two Delta-Sigma ADCs
with a multi-bit architecture. A Delta-Sigma ADC is an
oversampling converter that incorporates a built-in
modulator which is digitizing the quantity of charge
integrated by the modulator loop (see Figure 5-1). The
quantizer is the block that is performing the
analog-to-digital conversion. The quantizer is typically
1-bit, or a simple comparator which helps to maintain
the linearity performance of the ADC (the DAC
structure is, in this case, inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The MCP3911’s 5-level quantizer is a flash ADC
composed of four comparators arranged with equally
spaced thresholds and a thermometer coding. The
MCP3911 also includes proprietary 5-level DAC
architecture that is inherently linear for improved THD
figures.
4.14 Idle Tones
A Delta-Sigma converter is an integrating converter. It
also has a finite quantization step (LSB) which can be
detected by its quantizer. A DC input voltage that is
below the quantization step should only provide an all
zeros result since the input is not large enough to be
detected. As an integrating device, any Delta-Sigma
will show in this case idle tones. This means that the
output will have spurs in the frequency content that are
depending on the ratio between quantization step
voltage and the input voltage. These spurs are the
result of the integrated sub-quantization step inputs
that will eventually cross the quantization steps after a
long enough integration. This will induce an AC
frequency at the output of the ADC and can be shown
in the ADC output spectrum.
These idle tones are residues that are inherent to the
quantization process and the fact that the converter is
integrating at all times without being reset. They are
residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
are heavily signal dependent. They can degrade both
SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and thus difficult to filter from the actual input signal.
For power metering applications, idle tones can be very
disturbing because energy can be detected even at the
50 or 60 Hz frequency, depending on the DC offset of
the ADCs, while no power is really present at the
inputs. The only practical way to suppress or attenuate
idle tones phenomenon is to apply dithering to the
ADC. The idle tones amplitudes are a function of the
order of the modulator, the OSR and the number of
levels in the quantizer of the modulator. A higher order,
a higher OSR or a higher number of levels for the
quantizer will attenuate the idle tones amplitude.
THD dB() 10
HarmonicsPower
FundamentalPower
-----------------------------------------------------
⎝⎠
⎛⎞
log=
THD %() 100 10
THD dB()
20
------------------------
×
=
SFDR dB() 10
FundamentalPower
HighestSpurPower
-----------------------------------------------------
⎝⎠
⎛⎞
log=