Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 24 Bit SSOP 20

MCP3911

3.11 Oscillator And Master Clock Input

Pins (OSC1/CLKI, OSC2)

OSC1/CLKI and OSC2 provide the master clock

(MCLK) for the device. When CLKEXT=0, a resonant

crystal or clock source with a similar sinusoidal wave-

form must be placed across these pins to ensure

proper operation. The typical clock frequency specified

is 4 MHz. For proper operation, and for optimizing ADC

accuracy, AMCLK should be limited to the maximum

frequency defined in the Table 5- 3 in function of the

BOOST and PGA setting chosen. MCLK can take

larger values as long as the prescaler settings

(PRE<1:0>) limit AMCLK=MCLK/PRESCALE in the

defined range in the Table 5-3. Appropriate load

capacitance should be connected to these pins for

proper operation.

3.12 Chip Select (CS)

This pin is the SPI chip select that enables the serial

communication. When this pin is high, no

communication can take place. A chip select falling

edge initiates the serial communication and a chip

select rising edge terminates the communication. No

communication can take place even when CS

is low

when RESET

is low.

This input is Schmitt-triggered.

3.13 Serial Data Clock (SCK)

This is the serial clock pin for SPI communication.

Data is clocked into the device on the RISING edge of

SCK. Data is clocked out of the device on the FALLING

edge of SCK.

The MCP3911 interface is compatible with both SPI 0,0

and 1,1 modes. SPI modes can be changed during a

high time.

The maximum clock speed specified is 20 MHz.

This input is Schmitt triggered.

3.14 Serial Data Output (SDO)

This is the SPI data output pin. Data is clocked out of

the device on the FALLING edge of SCK.

This pin stays high impedance during the first

command byte. It also stays high impedance during the

whole communication for write commands and when

pin is high or when RESET pin is low. This pin is

active only when a read command is processed. Each

read is processed by packet of 8 bits.

3.15 Serial Data Input (SDI)

This is the SPI data input pin. Data is clocked into the

device on the RISING edge of SCK.

When CS

is low, this pin is used to communicate with a

series of 8-bit commands.

The interface is half-duplex (inputs and outputs do not

happen at the same time).

Each communication starts with a chip select falling

edge followed by an 8-bit command word entered

through the SDI pin. Each command is either a Read or

a Write command. Toggling SDI during a Read

command has no effect.

This input is Schmitt triggered.