Datasheet

MCP3911
DS22286A-page 2 © 2012 Microchip Technology Inc.
Functional block diagram
CH0+
CH0-
CH1+
CH1-
DUAL Δ–Σ ADC
ANALOG DIGITAL
SINC
3
+
SINC
1
-
+
PGA
-
+
PGA
Δ–Σ
Modulator
AMCLK
DMCLK/DRCLK
Phase
Shifter
Φ
PHASE <11:0>
DATA_CH0
<23:0>
MOD<7:0>
REFIN+/OUT
REFIN-
AVDD
AGND DGND
DVDD
MOD<3:0>
MOD<7:4>
POR
AVDD
Monitoring
Δ–Σ
Modulator
Vref+Vref-
VREFEXT
Voltage
Reference
Vref
+
-
POR
DVDD
Monitoring
SDO
SDI
SCK
Xtal Oscillator
MCLK
OSC1
OSC2
DR
RESET
Digital SPI
Interface
Clock
Generation
Modulator
Output Block
MDAT1
MDAT0
DMCLK
OSR<2:0>
PRE<1:0>
MODOUT<1:0>
CS
+
OFFCAL_CH0
<23:0>
GAINCAL_CH0
<23:0>
X
+
OFFCAL_CH1
<23:0>
GAINCAL_CH1
<23:0>
X
DATA_CH1
<23:0>
SINC
3
+
SINC
1