Datasheet

© 2012 Microchip Technology Inc. DS22286A-page 19
MCP3911
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Master Reset (RESET)
This pin is active low and places the entire chip in a
reset state when active.
When RESET
=0, all registers are reset to their default
value, no communication can take place, and no clock
is distributed inside the part, except in the input struc-
ture if MCLK is applied (if idle, then no clock is distrib-
uted). This state is equivalent to a POR state.
Since the default state of the ADCs is on, the analog
power consumption, when RESET
=0, is equivalent to
when RESET
=1. Only the digital power consumption is
largely reduced because this current consumption is
essentially dynamic and is reduced drastically when
there is no clock running.
All the analog biases are enabled during a reset so that
the part is fully operational just after a RESET
rising
edge, if the MCLK is applied during the rising edge. If
not applied, there is a small time after RESET where
the conversion may not be accurate corresponding to
the startup of the charge pump of the input structure.
This input is Schmitt triggered.
3.2 Digital V
DD
(DV
DD
)
DV
DD
is the power supply pin for the digital circuitry
within the MCP3911. This pin requires appropriate
bypass capacitors and should be maintained between
2.7V and 3.6V for specified operation.
3.3 Analog V
DD
(AV
DD
)
AV
DD
is the power supply pin for the analog circuitry
within the MCP3911. This pin requires appropriate
bypass capacitors and should be maintained to 2.7V
and 3.6V for specified operation.
3.4 ADC Differential Analog inputs
(CHn+/CHn-)
CH0- and CH0+, and CH1- and CH1+, are the two
fully-differential analog voltage inputs for the
Delta-Sigma ADCs.
Pin No.
SSOP
Pin No.
QFN
Symbol Function
1 18 RESET
Master Reset Logic Input Pin
219 DV
DD
Digital Power Supply Pin
320 AV
DD
Analog Power Supply Pin
4 1 CH0+ Non-Inverting Analog Input Pin for Channel 0
5 2 CH0- Inverting Analog Input Pin for Channel 0
6 3 CH1- Inverting Analog Input Pin for Channel 1
7 4 CH1+ Non-Inverting Analog Input Pin for Channel 1
8 5 AGND Analog Ground Pin, Return Path for internal analog circuitry
9 6 REFIN+/OUT Non-Inverting Voltage Reference Input and Internal Reference Output Pin
10 7 REFIN- Inverting Voltage Reference Input Pin
11 8 DGND Digital Ground Pin, Return Path for internal digital circuitry
12 9 MDAT1 Modulator Data Output Pin for Channel 1
13 10 MDAT0 Modulator Data Output Pin for Channel 0
14 11 DR
Data Ready Signal Output Pin
15 12 OSC1/CLKI Oscillator Crystal Connection Pin or External Clock Input Pin
16 13 OSC2 Oscillator Crystal Connection Pin
17 14 CS
Serial Interface Chip Select Pin
18 15 SCK Serial Interface Clock Input Pin
19 16 SDO Serial Interface Data Input Pin
20 17 SDI Serial Interface Data Input Pin
- 21 EP Exposed Thermal Pad. Must be connected to AGND.