MCP3911 3.3V Two-Channel Analog Front End Features Description • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters • 94.5 dB SINAD, -106.5 dBc Total Harmonic Distortion (THD) (up to 35th harmonic), 111 dB SFDR for Each Channel • 2.7V - 3.6V AVDD, DVDD • Programmable Data Rate up to 125 ksps - 4 MHz Maximum Sampling Frequency • Oversampling Ratio up to 4096 • Ultra Low Power Shutdown Mode with <2 µA • -122 dB Crosstalk between the Two Channels • Low Drift 1.
MCP3911 Functional block diagram REFIN+/OUT AVDD Voltage Reference + DVDD Vref REFIN- Clock Generation DMCLK/DRCLK Vref- Vref+ ANALOG CH0+ + CH0- PGA CH1+ + CH1- PGA DMCLK OSC1 OSC2 + X Phase PHASE <11:0> Shifter OFFCAL_CH1 GAINCAL_CH1 <23:0> <23:0> DATA_CH1 <23:0> Φ + MOD<7:4> OSR<2:0> PRE<1:0> OFFCAL_CH0 GAINCAL_CH0 <23:0> <23:0> DATA_CH0 <23:0> MOD<3:0> Δ–Σ Modulator Δ–Σ Modulator MCLK DIGITAL SINC3+ SINC1 DR SDO Digital SPI Interface X RESET SDI SCK CS SINC3+ SINC1 MO
MCP3911 1.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS † VDD ..................................................................... -0.3V to 4.0V Digital inputs and outputs w.r.t. AGND ................ --0.3V to 4.0V Analog input w.r.t. AGND ..................................... ....-2V to +2V VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................
MCP3911 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V, MCLK = 4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT=0, CLKEXT=1, AZ_FREQ=0, DITHER<1:0>=11, BOOST<1:0> = 10; VCM=0V; TA = -40°C to +125°C; VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz on both channels.
MCP3911 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V, MCLK = 4 MHz; PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT=0, CLKEXT=1, AZ_FREQ=0, DITHER<1:0>=11, BOOST<1:0> = 10; VCM=0V; TA = -40°C to +125°C; VIN = 1.2 VPP = 424 mVRMS @ 50/60 Hz on both channels.
MCP3911 1.2 SERIAL INTERFACE CHARACTERISTICS TABLE 1-2: SERIAL DC CHARACTERISTICS TABLE Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, CLOAD = 30pF, applies to all digital I/O. Sym Characteristics VIH High-level Input voltage VIL Low-level Input voltage ILI Input leakage current ILO Min Typ 0.7 DVDD — Max Units Test Conditions V Schmitt Triggered — 0.
MCP3911 TABLE 1-3: SERIAL AC CHARACTERISTICS TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at DVDD = 2.7 to 3.6V, TA = -40°C to +125°C, GAIN = 1, CLOAD = 30pF. Sym Characteristics Min tMODSU Modulator Mode Entry to Modulator Data Present tDRP Data Ready Pulse Low Time Typ Max Units — 100 ns 1/DMCLK — µs Test Conditions Note 1: This parameter is periodically sampled and not 100% tested.
MCP3911 tCSD CS tHI Mode 1,1 SCK tCLE fSCK tCSS tCSH tLO tCLD Mode 0,0 tSU SDI tHD MSB in LSB in HI-Z SDO FIGURE 1-2: Serial Input Timing Diagram. 1 / fD tDRP DR tDODR SCK SDO FIGURE 1-3: DS22286A-page 8 Data Ready Pulse / Sampling Timing Diagram. © 2012 Microchip Technology Inc.
MCP3911 H Waveform for tDIS Timing Waveform for tDO SCK CS VIH tDO 90% SDO SDO tDIS HI-Z 10% Timing Waveform for MDAT0/1 Modulator Output Function OSC1/CLKI tDOMDAT MDAT FIGURE 1-4: Timing Diagrams, continued. © 2012 Microchip Technology Inc.
MCP3911 NOTES: DS22286A-page 10 © 2012 Microchip Technology Inc.
MCP3911 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, AVDD = 3.
MCP3911 Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. Freq quency of Occurrence Freque ency of Occurrence Note: 104.5 15.3 15.4 15.4 15.4 15.5 15.5 15.5 15.5 15.6 15.6 106 107.5 109 110.5 112 113.5 115 Spurious Free Dynamic Range (dBFS) FIGURE 2-10: 15.4 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5 95.6 95.8 95.
MCP3911 Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25 °C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X.
MCP3911 Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3 V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. 120 110 100 90 80 70 60 50 40 30 20 10 0 Signal to Noise and Distortion Ratio (dB) Spurious Free Dynamic Range (dBFS) Note: Boost = 2x Boost = 0.66x Boost = 1x Boost = 0.
MCP3911 Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. 100 90 80 70 60 50 40 30 20 10 0 Signal to Noise and Distortion Ration (dB) 120 110 100 90 80 70 60 50 40 30 20 10 0 Channel 1 Channel 0 -6 -5 -4 -3 -2 -1 0 1 Input Signal Amplitude (dBFS) Spurious s Free Dyanmic Raneg (dBFS) FIGURE 2-25: Amplitude.
MCP3911 Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. 400 Cha annel 0 Offset (PV) 350 300 G=32 250 G=16 200 G=8 150 G=4 100 50 0 G=1 G=2 -50 -100 -50 -25 0 FIGURE 2-31: Temperature. 25 50 75 Temperature (°C) 100 125 150 Channel 0 Offset vs. FIGURE 2-34: Gain Error vs. Temperature. FIGURE 2-35: vs. Temperature.
MCP3911 Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS @ 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0; BOOST = 1X. 4.5 Frequency of Occurrence 4 AIDD, Boost = 2x 3.5 IDD (mA) 3 2.5 2 AIDD, Boost = 1x AIDD, Boost = 0.6x 1.5 5 1 AIDD, Boost = 0.5x 0.5 DIDD, All Boost Settings 0 0 3 6 9 12 15 18 21 Internal Voltage Reference Drift (ppm/C) VREF Drift Data Histogram 25 4 20 3.
MCP3911 NOTES: DS22286A-page 18 © 2012 Microchip Technology Inc.
MCP3911 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin No. SSOP Pin No.
MCP3911 The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±600 mV/GAIN with VREF=1.2V. The maximum differential voltage is proportional to the VREF voltage. The maximum absolute voltage, with respect to AGND, for each CHn+/- input pin is +/-1V with no distortion and ±2V with no breaking after continuous voltage. This maximum absolute voltage is not proportional to the VREF voltage. 3.
MCP3911 3.11 Oscillator And Master Clock Input Pins (OSC1/CLKI, OSC2) OSC1/CLKI and OSC2 provide the master clock (MCLK) for the device. When CLKEXT=0, a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. For proper operation, and for optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in the Table 5-3 in function of the BOOST and PGA setting chosen.
MCP3911 NOTES: DS22286A-page 22 © 2012 Microchip Technology Inc.
MCP3911 4.0 TERMINOLOGY AND FORMULAS This section defines the terms and formulas used throughout this data sheet. The following terms are defined: MCLK - Master Clock 4.1 MCLK - Master Clock This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT=0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT=1. See Figure 4-1. AMCLK - Analog Master Clock 4.
MCP3911 Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. TABLE 4-2: PRE <1:0> The following table describes the various combinations of OSR and PRESCALE and their associated AMCLK, DMCLK and DRCLK rates.
MCP3911 4.5 OSR - Oversampling Ratio 4.8 Integral Non-Linearity Error This is the ratio of the sampling frequency to the output data rate. OSR= DMCLK/DRCLK. The default OSR is 256, or with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4 MHz, fS = 1 MHz, fD = 3.90625 ksps. The following bits in the CONFIG register are used to change the oversampling ratio (OSR).
MCP3911 4.11 Total Harmonic Distortion (THD) The total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by the following equation. EQUATION 4-6: HarmonicsPower THD ( dB ) = 10 log ⎛ -----------------------------------------------------⎞ ⎝ FundamentalPower⎠ The THD calculation includes the first 35 harmonics for the MCP3911 specifications. The THD is usually only measured with respect to the 10 first harmonics.
MCP3911 4.15 Dithering In order to suppress, or attenuate, the idle tones present in any Delta-Sigma ADCs, dithering can be applied to the ADC. Dithering is the process of adding an error to the ADC feedback loop in order to “decorrelate” the outputs and “break” the idle tones behavior. Usually a random or pseudo-random generator adds an analog or digital error to the feedback loop of the Delta-Sigma ADC in order to ensure that no tonal behavior can happen at its outputs.
MCP3911 EQUATION 4-11: Δ VOUT CMRR ( dB ) = 20 log ⎛⎝ -----------------⎞⎠ Δ VCM input leakage currents can be observed for highly negative input voltages (typically below -0.6V referred to AGND). 4.20 Where VCM= (CHn+ + CHn-)/2 is the common-mode input voltage and VOUT is the equivalent input voltage that the output code translates to with the ADC transfer function. In the MCP3911 specification, VCM varies from -1V to +1V. 4.
MCP3911 ADC shutdown mode also effects the modulator output block, i.e., if MDAT of the channel in shutdown mode is enabled, this pin will provide a bitstream corresponding to a zero output (series of 0011 bits continuously repeated). When an ADC exits ADC shutdown mode, any phase delay present before shutdown was entered will still be present.
MCP3911 NOTES: DS22286A-page 30 © 2012 Microchip Technology Inc.
MCP3911 5.0 DEVICE OVERVIEW 5.1 Analog Inputs (CHn+/-) The MCP3911 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or Rogowski coils). Each input pin is protected by specialized ESD structures that are certified to pass 4.0 kV HBM and 200V MM contact charge. These structures allow bipolar ±2V continuous voltage with respect to AGND, to be present at their inputs without the risk of permanent damage.
MCP3911 modulator is still functional, however its stability is no longer guaranteed and therefore it is not recommended to exceed this limit (see FIGURE 2-24: “SINAD vs. Input Signal Amplitude.” for extended dynamic range performance limitations). The saturation point for the modulator is VREF/1.5 since the transfer function of the ADC includes a gain of 1.5 by default (independent from the PGA setting. See Section 5.6 “ADC Output Coding”). 5.3.3 MCLK.
MCP3911 5.3.4 AUTOZEROING FREQUENCY SETTING (AZ_FREQ) The MCP3911 modulators include an autozeroing algorithm to improve the offset error performance and greatly diminish 1/f noise in the ADC. This algorithm permits it to reach very high SNR and flattens the noise spectrum at the output of the ADC (see performance graphs Figure 2-1, Figure 2-2, Figure 2-3 and Figure 24).
MCP3911 Since the reset and shutdown SPI commands are asynchronous, the MDAT pins are resynchronized with DMCLK after each time the part goes out of reset and shutdown. This means that the first output of MDAT, after a soft reset or a shutdown, is always 0011 after the first DMCLK rising edge. The two MDAT output pins are in high impedance if the RESET pin is low. COMP COMP COMP COMP <0> <1> <3> <2> AMCLK DMCLK 5.
MCP3911 EQUATION 5-2: SETTING TIME OF THE ADC AS A FUNCTION OF DMCLK PERIODS SettlingTime ( DMCLKPeriods ) = 3 × OSR3 + ( OSR1 – 1 ) × OSR 3 The SINC1 filter following the SINC3 filter is only enabled for the high OSR settings. This SINC1 filter provides additional rejection at a low cost with little modification to the -3 dB bandwidth.
MCP3911 FIGURE 5-4: SINC Filter Frequency Response, OSR = 256, MCLK = 4 MHz, PRE<1:0> = 00. FIGURE 5-5: SINC Filter Frequency Response, OSR = 4096 (pink), OSR = 512 (blue), MCLK = 4 MHz, PRE<1:0> = 00. DS22286A-page 36 © 2012 Microchip Technology Inc.
MCP3911 5.6 ADC Output Coding In case of positive saturation (CHn+ - CHn- > VREF/ 1.5), the output is locked to 7FFFFF for 24 bit mode (7FFF for 16 bit mode). In case of negative saturation (CHn+ - CHn- <-VREF/1.5), the output code is locked to 800000 for 24-bit mode (8000 for 16 bit mode). The second order modulator, SINC3+SINC1 filter, PGA, VREF and analog input structure, all work together to produce the device transfer function for the analog to digital conversion, Equation 5-3.
MCP3911 TABLE 5-7: OSR = 64 OUTPUT CODE EXAMPLES ADC Output code (MSB First) 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 TABLE 5-8: 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 5.7 5.7.
MCP3911 5.7.3 TEMPERATURE COMPENSATION (VREFCAL REGISTER) 5.8 The MCP3911 contains an internal POR circuit that monitors both analog and digital supply voltages during operation. The typical threshold for a power-up event detection is 2.1 V ±5% and a typical start-up time (tPOR) of 50 µs. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.
MCP3911 5.9 RESET Effect On Delta-Sigma Modulator/SINC Filter When the RESET pin is logic low, both ADCs will be in Reset and output code 0x0000h. The RESET pin performs a hard reset (DC biases still on, part ready to convert) and clears all charges contained in the DeltaSigma modulators. The comparator’s output is 0011 for each ADC. The SINC filters are all reset, as well as their double output buffers. This pin is independent of the serial interface. It brings all the registers to the default state.
MCP3911 TABLE 5-9: PHASE VALUES WITH MCLK = 4 MHZ, OSR = 4096 Hex Delay (CH0 relative to CH1) 011111111111 0x7FF + 2047 µs 011111111110 0x7FE + 2046 µs 000000000001 0x001 + 1 µs 000000000000 0x000 0 µs 111111111111 0xFFF - 1 µs 100000000001 0x801 - 2048 µs 100000000000 0x800 -2048 µs Phase Register Value 5.11 When CLKEXT=1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock (see Figure 4-1).
MCP3911 5.12.1 DIGITAL OFFSET ERROR CALIBRATION The OFFCAL_CHn registers are 23-bit plus sign two’s complement register, which LSB value is the same as the Channel ADC Data. These two registers are then added bit-by-bit to the ADC output codes, if the EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL bit does not create any pipeline delay, the offset addition is instantaneous. For low OSR values, only the significant digits are added to the output (up to the resolution of the ADC.
MCP3911 6.0 6.1 SERIAL INTERFACE DESCRIPTION A5 A4 A3 A2 A1 A0 Overview The MCP3911 device is compatible with SPI Modes 0,0 and 1,1. Data is clocked out of the MCP3911 on the falling edge of SCK and data is clocked into the MCP3911 on the rising edge of SCK. In these modes, SCK can Idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent.
MCP3911 6.5 SPI MODE 1,1 – Clock Idle High, Read/Write Examples In this SPI mode, SCK idles high. For the MCP3911, this means that there will be a falling edge on SCK before there is a rising edge. Note: Changing from an SPI Mode 1,1 to an SPI Mode 0,0 is possible and can be done while CS pin is logic high.
MCP3911 6.6 SPI MODE 0,0 – Clock Idle Low, Read/Write Examples In this SPI mode, SCK idles low. For the MCP3911, this means that there will be a rising edge on SCK before there is a falling edge.
MCP3911 6.7 Continuous Communication, Looping on Address Sets If the user wishes to read back either of the ADC channels continuously, or both channels continuously, the internal address counter of the MCP3911 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS pin returns logic high.
MCP3911 CS SCK CH0 ADC ADDR/R SDI SDO CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte HiZ CH0 ADC MSB Old ADC data CH0 ADC Upper byte CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC CH0 ADC Upper byte New ADC data Middle byte Lower byte Upper byte Middle byte Lower byte Old ADC data DR These bytes are not present when WIDTH=0 (16-bit mode) FIGURE 6-6: CH0 ADC Old MSB data – Previous MSB data present on SDO until the data ready pulse upd
MCP3911 6.7.2 CONTINUOUS WRITE The following register sets are defined as types: Both ADCs are powered up with their default configurations, and begin to output data ready pulses immediately (RESET<1:0> and SHUTDOWN<1:0> bits are off by default). TABLE 6-2: Type The default output codes for both ADCs are all zeros. The default modulator output for both ADCs is ‘0011’ (corresponding to a theoretical zero voltage at the inputs). The default phase is zero between the two channels.
MCP3911 6.9 Data Ready Pin (DR) To signify when channel data is ready for transmission, the data ready signal is available on the Data Ready pin (DR) through an active-low pulse at the end of a channel conversion. The data ready pin outputs an active-low pulse with a period that is equal to the DRCLK clock period, and with a width equal to one DMCLK period. When not active-low, this pin can either be in highimpedance (when DR_HIZ = 0) or in a defined logic high state (when DR_HIZ = 1).
MCP3911 RESET RESET<0> or RESET<1> or SHUTDOWN<0> SHUTDOWN<1> DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR 3*DRCLK period DRCLK Period 1 DMCLK Period D5 DRCLK Period D6 D9 D4 D8 D16 D17 D3 D7 D14 D15 D2 D6 D12 D13 D6 D1 D5 D10 D11 D5 D6 D0 D4 D8 D9 D4 D5 D9 D7 D3 D7 D3 D4 D8 D6 D2 D6 D3 D7 D5 D1 D5 D6 D4 D0 D3 D4 D5 D3 D1 D
MCP3911 7.0 INTERNAL REGISTERS The addresses associated with the internal registers are listed below. A detailed description of the registers follows. All registers are split in 8-bit long registers, which can be addressed and read separately. Read and Write modes define the groups and types of registers for continuous read/write communication or looping on address sets as shown in Register 7-2.
MCP3911 .
MCP3911 7.1 CHANNEL REGISTERS - ADC CHANNEL DATA OUTPUT REGISTERS REGISTER 7-1: CHANNEL REGISTER Name Bits Address R/W CHANNEL0 24 0x00 R CHANNEL1 24 0x03 R The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with READ<1:0> bits). These registers are latched when an ADC read communication occurs.
MCP3911 7.2 MOD REGISTER - MODULATORS OUTPUT REGISTER MOD Register REGISTER 7-2: Name Bits Address Cof MOD 8 0x06 R/W The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on both ADCs. Each bit in this register corresponds to one comparator output on one of the channels. .
MCP3911 7.3 PHASE Register - Phase Configuration Register PHASE Register REGISTER 7-3: Name Bits Address Cof PHASE 16 0x07 R/W Any write to one of these two addresses (0x07 and 0x08) creates an internal reset and restart sequence.
MCP3911 7.
MCP3911 7.
MCP3911 bit 4:3 WIDTH<1:0> ADC Channel output data word width 11 = Both channels are in 24-bit mode(DEFAULT) 10 = Channel1 in 24-bit mode, Channel0 in 16-bit mode 01 = Channel1 in 16-bit mode, Channel0 in 24-bit mode 00 = Both channels are in 16-bit mode bit 2 EN_OFFCAL Enables or disables the 24-bit digital offset calibration on both channels 1 = Enabled; this mode does not add any group delay 0 = Disabled (DEFAULT) bit 1 EN_GAINCAL Enables or disables the 24-bit digital offset calibration on both cha
MCP3911 7.
MCP3911 bit 2 VREFEXT Internal Voltage Reference Shutdown Control 1 = Internal Voltage Reference Disabled 0 = Internal Voltage Reference Enabled (Default) bit 1 CLKEXT Internal Clock selection bits 1 = External clock drive by MCU on OSC1 pin (crystal oscillator disabled, no internal power consumption) (Default) 0 = Crystal oscillator is enabled. A crystal must be placed between OSC1 and OSC2 pins. bit 0 Not implemented, read as 0 7.
MCP3911 7.8 GAINCAL_CHn REGISTERS DIGITAL GAIN ERROR CALIBRATION REGISTERS REGISTER 7-8: GAINCAL_CHn REGISTERS Name Bits Address Cof GAINCAL_CH0 24 0x11 R/W GAINCAL_CH1 24 0x17 R/W R/W-0 R/W-0 R/W-0 GAINCAL_CHn GAINCAL_CHn GAINCAL_CHn <23> <22> <21> ... ...
MCP3911 7.9 VREFCAL Register – Internal Voltage Reference Temperature Coefficient Adjustment Register REGISTER 7-9: VREFCAL REGISTER Name Bits Address Cof VREFCAL 8 0x1A R/W This register is only for advanced users. This register should not be written unless the user wants to calibrate the temperature coefficient of the whole system or application. The default value of this register is set to 0x42.
MCP3911 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 20-Lead QFN (4x4x0.9 mm) PIN 1 Example: PIN 1 20-Lead SSOP (SS) 3911A0 e3 E/ML^^ 122256 Example: 3911A0 e3 E/SS^^ 1122256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
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MCP3911 APPENDIX A: REVISION HISTORY Revision A (March 2012) • Original Release of this Document. © 2012 Microchip Technology Inc.
MCP3911 NOTES: DS22286A-page 68 © 2012 Microchip Technology Inc.
MCP3911 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX X Device Address Options X Tape and Temperature Reel Range /XX Package Device: MCP3911A0: Two Channel Analog Font End Converter Address Options: XX A6 A5 A0* = 0 0 A1 = 0 1 A2 = 1 0 A3 = 1 1 * Default option.
MCP3911 NOTES: DS22286A-page 70 © 2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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