Datasheet

MCP3909
DS22025C-page 6  2006-2012 Microchip Technology Inc.
Serial Interface Timings (Note 4)
Data Ready Pulse Width
t
DR
4/MCLK
Reset Time
t
RST
100 — — ns
Output Data Rate
f
ADC
—MCLK/256—
Serial Clock Frequency f
CLK
—20MHzV
DD
= 5V
Window for serial mode entry
codes
t
WINDOW
——32/
MCLK
— Last bit must be clocked in
before this time.
Window start time for serial
mode entry codes
t
WINSET
1/MCLK — — — First bit must be clocked in
after this time.
Serial Clock High Time t
HI
— — 25 ns f
CLK
= 20 MHz
Serial Clock Low Time t
LO
— — 25 ns f
CLK
= 20 MHz
CS
Fall to First Rising CLK Edge t
SUCS
15 — — ns
Data Input Setup Time t
SU
10 — — ns
Data Input Hold Time t
HD
— — 10 ns
CS
Rise to Output Disable t
DIS
——150ns
CLK Rise to Output Data Valid t
DO
— — 30 ns
SDO Rise Time t
R
—2—ns
SDO Fall Time t
F
—2—ns
TIMING CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AV
DD
= DV
DD
= 4.5V to 5.5V,
A
GND
, D
GND
= 0V, MCLK = 3.58 MHz; T
A
= -40°C to +85°C.
Parameter Sym Min Typ Max Units Comment
Note 1: If output pulse period (t
FP
) falls below 984376*2 MCLK periods, then t
FW
= 1/2 t
FP
.
2: If output pulse period (t
HP
) falls below 322160*2 MCLK periods, then t
HW
= 1/2 t
HP
. When F2, F1, F0
equals 0,1,1, the HF
OUT
pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz.
3: Specified by characterization, not production tested.
4: Serial timings specified and production tested with 180 pF load.