Datasheet

 2006-2012 Microchip Technology Inc. DS22025C-page 27
MCP3909
5.4 Dual Channel Output Mode
This mode allows the user to retrieve the individual
channel information from the ADC outputs. The ADC
outputs of both channels are synchronized together
and their data ready is represented by the data ready
pulse on SDO. If the ADC output values are not clocked
out of the device, they will be over-written. A 32-bit data
word is given, each channel is 16 bits (15 bits + sign),
presented in 2's complement coding. Channel 1 comes
first then channel 0.
A data ready flag (DR) is output for every MCLK / 256
clock cycles and a new filter output value is ready. If the
dual channel output values are not clocked, and is not
clocked out of the device, they will be over-written.
The following formulas relate the channel input volt-
ages to their respective output code. The code locks to
+32767 on the positive side, and to -32768 on the
negative side.
EQUATION 5-2:
5.5 High-Pass Filter Control
There are two options for the channel output data. The
first options collects the channel data pre-high pass
filter, or the output of the SINC filter of the delta sigma
modulator. The second option collects the channel data
post high pass filter. It is important to note that the
HPF pin controls the state of the high pass filter for this
second option. If the HPF pin is low, the post high pass
filter mode will output all zero's. This HPF pin must be
high to access the post HPF data in the channel output
mode.
Channel 1 Code
V
IN+
V
IN-
–
V
REF
------------------------------------
32768 8.06
0.47
0.66
-----------



 =
Channel 0 Code
V
IN+
V
IN-
–
V
REF
------------------------------------



32768 8.06
0.66
0.47
-----------



PGA
 =
TABLE 5-3: CHANNEL OUTPUT MODE
CODING
Binary Decimal
0 111 1111 1111 1111 + 32,767
0 111 1111 1111 1110 + 32,766
0 000 0000 0000 0000 0
1 111 1111 1111 1111 -1
1 000 0000 0000 0001 - 32,767
1 000 0000 0000 0000 - 32,768