Datasheet

 2006-2012 Microchip Technology Inc. DS22025C-page 19
MCP3909
4.2 Analog Inputs
The MCP3909 analog inputs can be connected directly
to the current and voltage transducers (such as shunts
or current transformers). Each input pin is protected by
specialized ESD structures that are certified to pass
5 kV HBM and 500V MM contact charge. These struc-
tures also allow up to ±6V continuous voltage to be
present at their inputs without the risk of permanent
damage.
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin relative to A
GND
should be maintained in the ±1V
range during operation in order to ensure the measure-
ment error performance. The common-mode signals
should be adapted to respect both the previous condi-
tions and the differential input voltage range. For best
performance, the common-mode signals should be
referenced to A
GND
.
The current channel comprises a PGA on the front-end
to allow for smaller signals to be measured without
additional signal conditioning. The maximum differen-
tial voltage specified on Channel 0 is equal to ±470 mV/
Gain (see Table 4-1). The maximum peak voltage
specified on Channel 1 is equal to ±660 mV.
4.3 16-Bit Delta-Sigma A/D Converters
The ADCs used in the MCP3909 for both current and
voltage channel measurements are delta-sigma ADCs.
They comprise a second-order, delta-sigma modulator
using a multi-bit DAC and a third-order SINC filter. The
delta-sigma architecture is very appropriate for the
applications targeted by the MCP3909 because it is a
waveform-oriented converter architecture that can offer
both high linearity and low distortion performance
throughout a wide input dynamic range. It also creates
minimal requirements for the anti-aliasing filter design.
The multi-bit architecture used in the ADC minimizes
quantization noise at the output of the converters
without disturbing the linearity.
Each ADC has a 16-bit resolution, allowing wide input
dynamic range sensing. The oversampling ratio of both
converters is 64. Both converters are continuously con-
verting during normal operation. When the MCLR
pin is
low, both converters will be in Reset and output code
0x0000h. If the voltage at the inputs of the ADC is
larger than the specified range, the linearity is no longer
specified. However, the converters will continue to pro-
duce output codes until their saturation point is
reached. The DC saturation point is around 700 mV for
Channel 0 and 1V for Channel 1, using internal voltage
reference. The output code will be locked past the sat-
uration point to the maximum output code.
The clocking signals for the ADCs are equally distrib-
uted between the two channels in order to minimize
phase delays to less than 1 MCLK period (see
Section 3.2 “High-Pass Filter Input Logic Pin
(HPF)”). The SINC filters main notch is positioned at
MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing
the user to be able to measure wide harmonic content
on either channel. The data ready signals used for syn-
chronization of the part with a MCU will come at a rate
of MCLK/256 and a pipeline delay of 3 data readys is
required to settle the SINC 3rd order digital filter. The
magnitude response of the SINC filter is shown in
Figure 4-2.
FIGURE 4-2: SINC Filter Magnitude
Response (MCLK = 3.58 MHz).
TABLE 4-1: GAIN SELECTIONS
G1 G0 CH0 Gain
Maximum
CH0 Voltage
00 1±470mV
01 2±235mV
10 8±60mV
11 16 ±30 mV
-120
-100
-80
-60
-40
-20
0
0 5 10 15 20 25 30
Frequency (kHz)
Normal Mode Rejection (dB)