Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsData collecting ICsData acquisition IC - Analog front end (AFE) 24 Bit SSOP 28

MCP3903

bit 20:15 WIDTH_CHn ADC Channels output data word width control

1 = 24-bit mode for the corresponding channel

0 = 16-bit mode for the corresponding channel (default)

bit 14 DR_LTY: Data Ready Latency Control for DRA

, DRB, and DRC pins

1 = True “No Latency” Conversion,

data ready pulses after 3 DRCLK periods (DEFAULT)

0 = Unsettled Data is available after every DRCLK period

bit 13 DR_HIZ

: Data Ready Pin Inactive State Control for DRA, DRB, and DRC pins

1 = The Default state is a logic high when data is NOT ready

0 = The Default state is high impedance when data is NOT ready (DEFAULT)

bit 12 DR_LINK Data Ready Link Control

1 = Data Ready Link turned ON, all channels linked and data ready pulses from the most lagging ADC

are present on each DRn

0 = Data Ready Link tunred OFF (DEFAULT)

bit 11:10 DRC_MODE[1:0]

11 = Both Data Ready pulses from CH4 and CH5 are output on DRC

pin.

10 = Data Ready pulses from CH5 are output on DRC

pin. Data Ready pulses R from CH4 are not pres-

ent on the pin.

01 = Data Ready pulses from CH4 are output on DRC pin. Data Ready pulses from CH5 are not present

on the pin.

00 = Data Ready pulses from the lagging ADC channel between the two are output on DRC

pin. The

lagging ADC channel depends on the phase register and on the OSR. (DEFAULT)

bit 9:8 DRB_MODE[1:0]

11 = Both Data Ready pulses from CH2 and CH3 are output on DRB

pin.

10 = Data Ready pulses from CH3 are output on DRB

pin. Data Ready pulses from CH2 are not present

on the pin.

01 = Data Ready pulses from CH2 are output on DRB pin. Data Ready pulses from CH3 are not present

on the pin.

00 = Data Ready pulses from the lagging ADC channel between the two are output on DRB

pin. The

lagging ADC channel depends on the phase register and on the OSR. (DEFAULT)

bit 7:6 DRA_MODE[1:0]

11 = Both Data Ready pulses from CH0 and CH1 are output on DRA

pin.

10 = Data Ready pulses from CH1 are output on DRA

pin. Data Ready pulses from CH0 are not present

on the pin.

01 = Data Ready pulses from CH0 are output on DRA pin. Data Ready pulses from CH1 are not present

on the pin.

00 = Data Ready pulses from the lagging ADC channel between the two are output on DRA

pin. The

lagging ADC channel depends on the phase register and on the OSR. (DEFAULT)

bit 5:0 DRSTATUS_CHn: Data Ready Status

1 = Data Not Ready (default)

0 = Data Ready