Datasheet

© 2011 Microchip Technology Inc. DS25048B-page 39
MCP3903
7.2 Mod Register
The MOD register contains the most recent modulator
data output. The default value corresponds to an
equivalent input of 0V on each ADC. Each bit in this
register corresponds to one comparator output on one
of the channels.
This register should be used as a read-only register.
(Note 1). This register is updated at the refresh rate of
DMCLK (typically 1 MHz with MCLK = 4 MHz). The
default state for this register is
001100110011001100110011.
TABLE 7-4: MODULATOR OUTPUT
REGISTER
Name Bits Address Cof
MOD 24
0x06
R/W
REGISTER 7-2: MOD REGISTER
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1
COMP3_CH5 COMP2_CH5 COMP1_CH5 COMP0_CH5 COMP3_CH4 COMP2_CH4 COMP1_CH4 COMP0_CH4
bit 23 bit 16
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1
COMP3_CH3 COMP2_CH3 COMP1_CH3 COMP0_CH3 COMP3_CH2 COMP2_CH2 COMP1_CH2 COMP0_CH2
bit 15 bit 8
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1
COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH1 COMP2_CH0 COMP1_CH0 COMP0_CH0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 23:20 COMPn_CH5: Comparator Outputs from ADC Channel 5
bit 19:16 COMPn_CH4: Comparator Outputs from ADC Channel 4
bit 15:12 COMPn_CH3: Comparator Outputs from ADC Channel 3
bit 11:8 COMPn_CH2: Comparator Outputs from ADC Channel 2
bit 7:4 COMPn_CH1: Comparator Outputs from ADC Channel 1
bit 3:0 COMPn_CH0: Comparator Outputs from ADC Channel 0