Datasheet

MCP3903
DS25048B-page 34 © 2011 Microchip Technology Inc.
FIGURE 6-7: Standard Device Operation.
6.10 Data Ready Pulses (DRn)
To ensure that all channel ADC data are present at the
same time for SPI read, regardless of phase delay set-
tings for either or both channels, there are two sets of
latches in series with both the data ready and the ‘read
start’ triggers.
The first set of latches holds each output when data is
ready and latches both outputs together when
DRMODE<1:0>=00. When this mode is on, both ADCs
work together and produce one set of available data
after each data ready pulse (that corresponds to the
lagging ADC data ready). The second set of latches
ensures that when reading starts on an ADC output, the
corresponding data is latched so that no data
corruption can occur.
If an ADC read has started, in order to read the
following ADC output, the current reading needs to be
completed (all bits must be read from the ADC output
data registers).
6.10.1 DATA READY PINS (DRn) CONTROL
USING DRn_MODE BITS
There are four modes that control the data ready
pulses, and these modes are set with the
DRn_MODE<1:0> bits in the STATUS/COM register.
For power metering applications,
DRn_MODE<1:0>=00 is recommended (default
mode).
The position of data ready pulses vary with respect to
this mode, to the OSR and to the PHASE settings:
• DRn_MODE<1:0> = 11: Both Data Ready pulses
from ADC Channel 0/2/4 and ADC Channel 1/3/5
are output on DR pin.
• DRn_MODE<1:0> = 10: Data Ready pulses from
ADC Channel 1/3/5 are output on the correspond-
ing DRn pin. Data Ready pulses from ADC Chan-
nel 0/2/4 are not present on the pin.
• DRn_MODE<1:0> = 01: Data Ready pulses from
ADC Channel 0/2/4 are output on the correspond-
ing DRn pin. Data Ready pulses from ADC Chan-
nel 1/3/5 are not present on the pin.
• DRn_MODE<1:0> = 00: (Recommended, and
Default Mode). Data Ready pulses from the
lagging ADC between the two are output on DR
pin. The lagging ADC depends on the phase
register and on the OSR. In this mode the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready.
6.10.2 DR PULSES WITH SHUTDOWN OR
RESET CONDITIONS
There will be no data ready pulses if
DRn_MODE<1:0>=00 when either one or both of the
ADCs of the corresponding pair are in reset or shut-
down. In Mode 00, a data ready pulse only happens
when both ADCs of the corresponding pair are ready.
Any data ready pulse will correspond to one data on
both ADCs. The two ADCs are linked together and act
as if there was only one channel with the combined
data of both ADCs. This mode is very practical when
both ADC channel data retrieval and processing need
to be synchronized, as in power metering applications.
Figure 6-8 represents the behavior of the data ready
pin with the different DRn_MODE and DR_LTY
configurations, while shutdown or resets are applied.
1 / f
DATA
1 / f
LINE
DRn
1 / f
DATA
OSC1/MCLKI
CS
SCK
SDI
SPI
SDO
Note: If DRn_MODE<1:0>=11, the user will still
be able to retrieve the data ready pulse for
the ADC not in shutdown or reset, i.e. only
1 ADC channel needs to be awake.