Datasheet

MCP3903
DS25048B-page 14 © 2011 Microchip Technology Inc.
3.0 PIN DESCRIPTION
TABLE 3-1: PIN FUNCTION TABLE
3.1 RESET
This pin is active low and places the entire chip in a
reset state when active.
When RESET
=0, all registers are reset to their default
value, no communication can take place, no clock is
distributed inside the part. This state is equivalent to a
POR state.
Since the default state of the ADCs is on, the analog
power consumption when RESET
= 0 is equivalent to
when RESET
= 1. Only the digital power consumption
is largely reduced because this current consumption is
essentially dynamic and is reduced drastically when
there is no clock running. All the analog biases are
enabled during a reset so that the part is fully
operational just after a RESET
rising edge. This input
is Schmitt triggered.
3.2 Digital V
DD
(DV
DD
)
DV
DD
is the power supply pin for the digital circuitry
within the MCP3903. This pin requires appropriate
bypass capacitors and should be maintained between
2.7V and 3.6V for specified operation.
Pin No. Symbol Function
1AV
DD
Analog Power Supply Pin
2 CH0+ Non-Inverting Analog Input Pin for Channel 0
3 CH0- Inverting Analog Input Pin for Channel 0
4 CH1- Inverting Analog Input Pin for Channel 1
5 CH1+ Non-Inverting Analog Input Pin for Channel 1
6 CH2+ Non-Inverting Analog Input Pin for Channel 2
7 CH2- Inverting Analog Input Pin for Channel 2
8 CH3- Inverting Analog Input Pin for Channel 3
9 CH3+ Non-Inverting Analog Input Pin for Channel 3
10 CH4+ Non-Inverting Analog Input Pin for Channel 4
11 CH4- Inverting Analog Input Pin for Channel 4
12 CH5- Inverting Analog Input Pin for Channel 5
13 CH5+ Non-Inverting Analog Input Pin for Channel 5
14 REFIN+/OUT Non-Inverting Voltage Reference Input and Internal Reference Output Pin
15 REFIN- Inverting Voltage Reference Input Pin
16 A
GND
Analog Ground Pin, Return Path for internal analog circuitry
17 D
GND
Digital Ground Pin, Return Path for internal digital circuitry
18 DR
A Data Ready Signal Output for channels pair A
19 DR
B Data Ready Signal Output for channels pair B
20 DR
C Data Ready Signal Output for channels pair C
21 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin
22 OSC2 Oscillator Crystal Connection Pin
23 CS
Chip Select for Serial Interface
24 SCK Serial Interface Clock Pin
25 SDO Serial Interface Data Output Pin
26 SDI Serial Interface Data Input Pin
27 RESET
Master Reset Logic Input Pin
28 DV
DD
Digital Power Supply Pin