MCP3903 Six Channel Delta Sigma A/D Converter Features Description • Six Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture • 91 dB SINAD, -100 dBc Total Harmonic Distortion (THD) (up to 35th harmonic), 102 dB Spurious-free Dynamic Range (SFDR) for Each Channel • Programmable Data Rate up to 64 ksps • Ultra Low-Power Shutdown Mode with <2 μA • -115 dB Crosstalk Between any Two Channels • Low Drift Internal Voltage Reference: 5 ppm/°C • Differential
MCP3903 Functional Block Diagram REFIN/OUT+ REFIN - AVDD DVDD Voltage VREFEXT Reference + VREF - AMCLK DMCLK/DRCLK VREF- VREF+ ANALOG DIGITAL DMCLK SINC3 CH0+ + CH0- PGA Δ -Σ Modulator Φ CH1+ + CH1- PGA Clock Generation Xtal Oscillator MCLK OSC1 OSC2 OSR<1:0> PRE<1:0> DATA_CH0<23:0> Phase Shifter PHASEA <7:0> DRA DATA_CH1<23:0> Δ -Σ Modulator SINC3 DUAL DS ADC SINC3 CH2+ + CH2- PGA Δ -Σ Modulator Φ CH3+ + CH3- PGA DATA_CH2<23:0> Phase Shifter PHASEB <7:0> DATA_CH3<2
MCP3903 1.0 ELECTRICAL CHARACTERISTICS 1.1 RELIABILITY TARGETS ABSOLUTE MAXIMUM RATINGS † The Reliability Targets section includes the absolute maximum ratings for the device, defining the values that will cause no long term damage regardless of duration. VDD ................................................................................... 7.0V Digital inputs and outputs w.r.t. AGND ........-0.6V to VDD +0.6V Analog input w.r.t. AGND..................................... ....-6V to +6V VREF input w.
MCP3903 ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) TABLE 1-1: Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to 3.6V, Internal VREF, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C, GAIN = 1, VIN = 1VPP = 353mVRMS @ 50/60 Hz. Param. Num. Symbol Characteristic A011 CHn+- Analog Input Absolute Voltage A012 AIN Analog Input Leakage Current A013 (CHn+CHn-) A014 VOS A015 Min.
MCP3903 TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to 3.6V, Internal VREF, MCLK = 4 MHz;PRESCALE = 1; OSR = 64; fS = 1 MHz; fD = 15.625 ksps; TA = -40°C to +125°C, GAIN = 1, VIN = 1VPP = 353mVRMS @ 50/60 Hz. Param. Num. A028 Symbol MCLK Characteristic Master Clock Frequency Range Min. Typ. Max. Units 1 — 16.
MCP3903 1.2 SERIAL INTERFACE CHARACTERISTICS SERIAL INTERFACE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to 3.6V, -40°C < TA <+125°C, CLOAD = 30 pF. Parameters Sym Min Typ Max Units Conditions Serial Clock frequency fSCK — — 10 CS setup time tCSS 50 — — ns 2.7 ≤ DVDD < 3.6 — — ns 2.7 ≤ DVDD < 3.6 MHz 2.7 ≤ DVDD < 3.
MCP3903 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to 3.3 V.
MCP3903 H 1 / DRCLK DR tDRP tDODR SCK SDO FIGURE 1-3: Data Ready Pulse Timing Diagram. H Timing Waveform for tDIS Timing Waveform for tDO SCK CS VIH tDO 90% SDO SDO tDIS HI-Z 10% Timing Waveform for MDAT0/1 Modulator Output OSC1/CLKI tDOMDAT MDAT0/1 FIGURE 1-4: Specific Timing Diagrams.
MCP3903 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, AVDD = 5.
MCP3903 Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. SINAD NAD (dB) B) . 100 95 90 85 80 75 70 65 60 55 50 OSR = 256 OSR = 64 OSR = 32 1 FIGURE 2-7: Spectral Response. Dithering ON 100 Dithering OFF 80 60 40 20 0 32 64 128 256 Oversampling Ratio (OSR) FIGURE 2-8: Spurious Free Dynamic Range vs Oversampling Ratio.
MCP3903 Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. . 120 fs=15.625KHz OSR 64 OSR=64 -70 -80 80 Dithering OFF -90 -100 Dithering ON 40 -120 0 50 -40 100 200 500 1000 2000 Input Frequency (Hz) 0 fs=15.625KHz OSR=64 -20 -20 0 25 45 85 Temperature (°C) 105 125 FIGURE 2-16: Signal-to-Noise and Distortion vs. Temperature. 90 80 70 60 50 40 30 20 10 0 -10 0.
MCP3903 G=8 G=1 G=16 G=2 G=4 G=32 -40 -20 FIGURE 2-19: (Channel 0). 2.355 2.350 2.345 2.340 -40 -20 FIGURE 2-22: vs. Temperature. 0 25 45 85 Temperature (°C) 105 125 Internal Voltage Reference 2.35473 CH1 1.40 1 40 CH3 1.20 1.00 1 00 0.80 2.360 105 125 Offset Error vs. Temperature 1.60 Offsett Errorr (mV) 0 25 45 85 Temperature (°C) Int. Voltage e Reference rence (V) 1.40 1.20 1 20 1.00 0.80 0.60 0.40 0.20 0.00 0 00 -0.20 -0.40 CH2 CH0 CH5 0.60 0 60 0.40 CH4 0.20 0.
MCP3903 INL L (ppm) m) Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 3.3 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 50 40 30 20 10 0 10 -10 -20 30 -30 -40 -50 -0.5 CH0 CH1 -0.25 0 Input Voltage (V) INL (ppm) FIGURE 2-25: (Dithering OFF). 50 40 30 20 10 0 10 -10 -20 30 -30 -40 -50 -0.5 IDD D (mA)) 0.5 Integral Non-Linearity CH0 CH1 -0.25 FIGURE 2-26: (Dithering ON). 9 8 7 6 5 4 3 2 1 0 0.25 0 0.25 Input Voltage (V) 0.
MCP3903 3.0 PIN DESCRIPTION TABLE 3-1: 3.1 PIN FUNCTION TABLE Pin No.
MCP3903 3.3 Analog VDD (AVDD) AVDD is the power supply pin for the analog circuitry within the MCP3903. This pin requires appropriate bypass capacitors and should be maintained to 5V ±10% for specified operation. 3.4 ADC Differential Analog Inputs(CHn+/CHn-) CHn- and CHn+, are the two fully-differential analog voltage inputs for the Delta-Sigma ADCs. There are six channels in total grouped in three channel pairs. 3.
MCP3903 3.10 Oscillator And Master Clock Input Pins (OSC1/CLKI, OSC2) OSC1/CLKI and OSC2 provide the master clock for the device. When CLKEXT = 0 (Default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. However, the clock frequency can be 1 MHz to 5 MHz without disturbing ADC accuracy. With the current boost circuit enabled, the master clock can be used up to 8.
MCP3903 4.0 TERMINOLOGY AND FORMULAS This section defines the terms and formulas used throughout this data sheet. The following terms are defined: MCLK - Master Clock AMCLK - Analog Master Clock 4.2 AMCLK - Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two sigma-delta modulators.
MCP3903 Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. TABLE 4-2: PRE <1:0> The following table describes the various combinations of OSR and PRESCALE and their associated AMCLK, DMCLK and DRCLK rates. DEVICE DATA RATES IN FUNCTION OF MCLK, OSR, AND PRESCALE OSR <1:0> OSR AMCLK DMCLK DRCLK DRCLK (ksps) MCLK/8 MCLK/32 MCLK/8192 0.
MCP3903 4.8 Integral Non-Linearity Error 4.11 Total Harmonic Distortion (THD) Integral non-linearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. The total harmonic distortion is the ratio of the output harmonics power to the fundamental signal power for a sinewave input and is defined by the following equation.
MCP3903 4.13 MCP3903 Delta-Sigma Architecture The MCP3903 incorporates six Delta-Sigma ADCs with a multi-bit digital to analog converter as quantizer. A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator which is digitizing the quantity of charge integrated by the modulator loop (see Figure 5-1). The quantizer is the block that is performing the analog-to-digital conversion.
MCP3903 4.16 Crosstalk The crosstalk is defined as the perturbation caused by one ADC channel on the other ADC channel. It is a measurement of the isolation between the six ADCs present in the chip. This measurement is a two-step procedure: 1. 2. Measure one ADC input with no perturbation on any other ADC (ADC inputs shorted). Measure the same ADC input with a perturbation sine wave signal on the other ADC at a certain predefined frequency.
MCP3903 A data ready pulse will not be generated by any ADC while in reset mode. When an ADC exists ADC reset mode, any phase delay present before reset was entered will still be present. If one ADC was not in reset, the ADC leaving reset mode will automatically resynchronize the phase delay relative to the other ADC channel, per the phase delay register block and give data ready pulses accordingly. If an ADC is placed in Reset mode while the other is converting, it is not shutting down the internal clock.
MCP3903 5.0 DEVICE OVERVIEW 5.3 5.1 Analog Inputs (CHn+/-) 5.3.1 The MCP3903 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or Rogowski coils). Each input pin is protected by specialized ESD structures that are certified to pass 5 kV HBM and 500V MM contact charge. These structures allow bipolar ±6V continuous voltage with respect to AGND, to be present at their inputs without the risk of permanent damage.
MCP3903 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT For a specified voltage reference value of 2.4V, the modulator specified differential input range is ±500 mV. The input range is proportional to VREF and scales according to the VREF voltage. This range ensures the stability of the modulator over amplitude and frequency. Outside of this range, the modulator is still functional, however its stability is no longer guaranteed and therefore it is not recommended to exceed this limit.
MCP3903 SINC3 Filter 5.4 All ADCs present in the MCP3903 include a decimation filter that is a third-order sinc (or notch) filter. This filter processes the multi-bit bitstream into 16 or 24 bits words (depending on the WIDTH configuration bit). The settling time of the filter is 3 DMCLK periods. It is recommended to discard unsettled data to avoid data corruption which can be done easily by setting the DR_LTY bit high in the STATUS/COM register.
MCP3903 5.5 In case of positive saturation (CHn+ - CHn- > VREF/3), the output is locked to 7FFFFF for 24 bit mode (7FFF for 16 bit mode). In case of negative saturation (CHn+ - CHn- <-VREF/3), the output code is locked to 800000 for 24-bit mode (8000 for 16 bit mode). ADC OUTPUT CODING The second order modulator, SINC3 filter, PGA, VREF and analog input structure all work together to produce the device transfer function for the analog to digital conversion, shown in Equation 5-3.
MCP3903 TABLE 5-5: OSR = 64 OUTPUT CODE EXAMPLES ADC Output code (MSB First) 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 TABLE 5-6: 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 5.6 5.6.
MCP3903 5.7 Power-on Reset 5.8 The MCP3903 contains an internal POR circuit that monitors analog supply voltage AVDD during operation. The typical threshold for a power-up event detection is 4.2V ±5%. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF ceramic and 10 µF tantalum) should be mounted as close as possible to the AVDD pin, providing additional transient immunity.
MCP3903 5.9.1 PHASE DELAY LIMITS 5.10 The Phase delay can only go from -OSR/2 to +OSR/2 - 1. This sets the fine phase resolution. The phase register is coded with 2's complement. If larger delays between the two channels from the same pair are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks.
MCP3903 6.0 SERIAL INTERFACE DESCRIPTION 6.1 OVERVIEW The default device address bits are 01. A read on undefined addresses will give an all zeros output on the first and all subsequent transmitted bytes. A write on an undefined address will have no effect and will not increment the address counter either. The MCP3903 device is compatible with SPI modes 0,0 and 1,1. Data is clocked out of the MCP3903 on the falling edge of SCK, and data is clocked into the MCP3903 on the rising edge of SCK.
MCP3903 CS DATA TRANSITIONS ON THE FALLING EDGE MCU AND MCP3901 LATCH BITS ON THE RISING EDGE SCK 1 SDI 32 A6 A5 A4 A3 A2 A1 A0 R/W HI-Z SDO HI-Z D23 22 21 20 19 18 17 16 D15 D07 06 05 04 03 02 01 00 D23 (OF ADDRESS + 1 DATA) HI-Z (ADDRESS) 24 BIT DATA Note: FIGURE 6-2: Device Read (SPI MODE 0,0 - Clock Idles Low).
MCP3903 CS DATA TRANSITIONS ON THE FALLING EDGE MCU AND MCP3901 LATCH BITS ON THE RISING EDGE 32 1 SCK A6 A5 A4 A3 A2 A1 SDI A0 R/W 23 22 20 19 18 17 D16 D08 D7 D6 D5 D4 D3 D2 D1 D0 (ADDRESS) DATA HI-Z SDO HI-Z HI-Z FIGURE 6-5: 6.7 21 Device Write (SPI Mode 1,1 - Clock Idles High). The STATUS/COM register contains the loop settings for the internal address counter (READ<1:0>).
MCP3903 6.7.1 CONTINUOUS READ All ADCs are powered up with their default configurations, and begin to output data ready pulses immediately (RESET<5:0> and SHUTDOWN<5:0> bits are off by default). The default output codes for both ADCs are all zeros.The default modulator output for both ADCs is 0011 (corresponding to a theoretical zero voltage at the inputs). The default phase is zero between the two channels.
MCP3903 CS • DRn_MODE<1:0> = 11: Both Data Ready pulses from ADC Channel 0/2/4 and ADC Channel 1/3/5 are output on DR pin. • DRn_MODE<1:0> = 10: Data Ready pulses from ADC Channel 1/3/5 are output on the corresponding DRn pin. Data Ready pulses from ADC Channel 0/2/4 are not present on the pin. • DRn_MODE<1:0> = 01: Data Ready pulses from ADC Channel 0/2/4 are output on the corresponding DRn pin. Data Ready pulses from ADC Channel 1/3/5 are not present on the pin.
MCP3903 RESET RESET<0> or SHUTDOWN<0> RESET<1> or SHUTDOWN<1> DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR 3*DRCLK period DRCLK period 1 DMCLK period D6 DRCLK period D5 D9 D4 D8 D16 D17 D3 D7 D14 D15 D2 D6 D12 D13 D6 D1 D5 D10 D11 D5 D6 D0 D4 D8 D9 D4 D5 D9 D7 D3 D7 D3 D4 D8 D6 D2 D6 D3 D7 D5 D1 D5 D6 D4 D0 D3 D4 D5 D3 D1 D2 D2 D4 D9 D2 D0 D1 D2 D3 D8 D1 D0 D1 D2 D7 D0
MCP3903 6.11 DATA READY PULSE WITH PHASE DELAY To ensure that both channel ADC data from the same pair are present at the same time for SPI read, regardless of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the reading start triggers. The first latch is set on whichever channel is the lagging channel (relative to the other channel, in a single channel pair).
MCP3903 7.0 INTERNAL REGISTERS The addresses associated with the internal registers are listed below. All registers are 24 bits long and can be addressed separately. A detailed description of the registers follows. TABLE 7-1: .
MCP3903 REGISTER 7-1: CHANNEL REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 D23 (MSB) D22 D21 D20 D19 D18 D17 D16 bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 D15 D14 D13 D12 D11 D10 D9 D8 bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 D7 D6 D5 D4 D3 D2 D1 D0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23:0 x = Bit is unknown 24-bit ADC output dat
MCP3903 7.2 The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on each ADC. Each bit in this register corresponds to one comparator output on one of the channels. Mod Register TABLE 7-4: MODULATOR OUTPUT REGISTER Name Bits Address Cof This register should be used as a read-only register. MOD 24 0x06 R/W (Note 1). This register is updated at the refresh rate of DMCLK (typically 1 MHz with MCLK = 4 MHz).
MCP3903 7.3 The reference channel is the odd channel (Channel 1/ 3/5). When PHASEn<7:0> is positive, Channel 0/2/4 is lagging versus channel 1/3/5 otherwise it is leading. Phase Register TABLE 7-5: PHASE REGISTER Name Bits Address Cof The delay is calculated by the following formula: PHASE 24 0x07 R/W Delay = PHASE Register Code / DMCLK. The phase register is composed of three bytes: PHASEC<7:0>, PHASEB<7:0>, PHASEA<7:0>.
MCP3903 7.
MCP3903 7.5 STATUS/COM Register - Status and Communication Register TABLE 7-7: STATUS/COM Register Name Bits Address Cof STATUS/COM 24 0x09 R/W 7.5.1 DATA READY LATENCY - DR_LTY This bit determines if the data ready pulses correspond to settled data or unsettled data from each SINC3 filter. Unsettled data will provide data ready pulses every DRCLK period. Settled data will wait for 3 DRCLK periods before giving data ready pulses and will then give data ready pulses every DRCLK period. 7.5.
MCP3903 REGISTER 7-5: STATUS/COM REGISTER (CONTINUED) bit 20:15 WIDTH_CHn ADC Channels output data word width control 1 = 24-bit mode for the corresponding channel 0 = 16-bit mode for the corresponding channel (default) bit 14 DR_LTY: Data Ready Latency Control for DRA, DRB, and DRC pins 1 = True “No Latency” Conversion, data ready pulses after 3 DRCLK periods (DEFAULT) 0 = Unsettled Data is available after every DRCLK period bit 13 DR_HIZ: Data Ready Pin Inactive State Control for DRA, DRB, and DRC
MCP3903 7.
MCP3903 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 28-Lead SSOP (5.30 mm) Example MCP3903 E/SS e3 1124256 28-Lead SSOP (5.30 mm) Example MCP3903 I/SS e3 1124256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free.
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MCP3903 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
MCP3903 DS25048B-page 48 © 2011 Microchip Technology Inc.
MCP3903 APPENDIX A: REVISION HISTORY Revision B (July 2011) • Added Section 2.0, Typical Performance Curves, with characterization graphs. Revision A (June 2011) • Original data sheet for the MCP3903 device. © 2011 Microchip Technology Inc.
MCP3903 NOTES: DS25048B-page 52 © 2011 Microchip Technology Inc.
MCP3903 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X Device Device: X Tape and Temperature Reel Range MCP3903: /XX Package Six Channel ΔΣ A/D Converter * Default option.
MCP3903 NOTES: DS25048B-page 54 © 2011 Microchip Technology Inc.
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