Datasheet

MCP3901
DS22192D-page 36 © 2011 Microchip Technology Inc.
6.7 Continuous Communication,
Looping on Address Sets
If the user wishes to read back either of the ADC
channels continuously, or both channels continuously,
the internal address counter of the MCP3901 can be
set to loop on specific register sets. In this case, there
is only one control byte on SDI to start the
communication. The part stays within the same loop
until CS
returns high.
This internal address counter allows the following
functionality:
Read one ADC channel’s data continuously
Read both ADC channel’s data continuously (both
ADC data can be independent or linked with
DRMODE settings)
Continuously read the entire register map
Continuously read each separate register
Continuously read all Configuration registers
Write all Configuration registers in one
communication (see Figure 6-7)
The STATUS/COM register contains the loop settings
for the internal address counter (READ<1:0>). The
internal address counter can either stay constant
(READ<1:0> = 00) and continuously read the same
byte, or it can auto-increment and loop through the
register groups defined below (READ<1:0> = 01),
register types (READ<1:0> = 10) or the entire register
map (READ<1:0> = 11).
Each channel is configured independently as either a
16-bit or 24-bit data word, depending on the setting of
the corresponding WIDTH bit in the CONFIG1 register.
For continuous reading, in the case of WIDTH = 0
(16-bit), the lower byte of the ADC data is not accessed
and the part jumps automatically to the following
address (the user does not have to clock out the lower
byte since it becomes undefined for WIDTH = 0).
Figure 6-6 represents a typical, continuous read
communication with the default settings (DRMODE<1:0>
= 00, READ<1:0> = 10) for both WIDTH settings. This
configuration is typically used for power metering
applications.
FIGURE 6-6: Typical Continuous Read Communication.
CH0 ADC
ADDR/R
CS
SCK
SDI
CH0 ADC
Upper byte
SDO
CH0 ADC
Middle byte
CH0 ADC
Lower byte
DR
CH1 ADC
Upper byte
CH1 ADC
Middle byte
CH1 ADC
Lower byte
CH0 ADC
Upper byte
CH0 ADC
Middle byte
CH0 ADC
Lower byte
CH1 ADC
Upper byte
CH1 ADC
Middle byte
CH1 ADC
Lower byte
These bytes are not present when WIDTH=0 (16-bit mode)