MCP3901 Two-Channel Analog Front End Features Description • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture • 91 dB SINAD, -104 dBc Total Harmonic Distortion (THD) (up to 35th harmonic), 109 dB Spurious-free Dynamic Range (SFDR) for Each Channel • Programmable Data Rate up to 64 ksps • Ultra Low-Power Shutdown mode with <2 µA • -133 dB Crosstalk Between the Two Channels • Low Drift Internal Voltage Reference: 12 ppm/°C • Differential Voltage
MCP3901 Functional Block Diagram REFIN/OUT+ REFIN - AVDD DVDD Voltage VREFEXT Reference + VREF - AMCLK DMCLK/DRCLK VREF- VREF+ ANALOG DIGITAL Clock Generation DMCLK Xtal Oscillator OSC1 MCLK OSC2 OSR<1:0> PRE<1:0> SINC3 CH0+ + CH0- PGA DATA_CH0<23:0> DR SDO Δ -Σ Modulator Phase Shifter Φ CH1+ + CH1- PGA PHASE <7:0> DATA_CH1<23:0> Δ -Σ Modulator POR AVDD Monitoring MOD<7:0> POR AGND RESET SDI SCK CS SINC3 DUAL DS ADC SDN<1:0>, RESET<1:0>, GAIN<7:0> DS22192D-page 2 Digital SPI I
MCP3901 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † VDD ...................................................................................7.0V Digital inputs and outputs w.r.t. AGND ........ -0.6V to VDD +0.6V Analog input w.r.t. AGND ..................................... ....-6V to +6V VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................
MCP3901 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5V; -40°C < TA < +85°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.
MCP3901 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5V; -40°C < TA < +85°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS = 333 mVRMS @ 50/60 Hz Parameters Symbol Min Typical Max Units Conditions AC Power Supply Rejection AC PSRR — -77 — dB AVDD and DVDD = 5V + 1 VPP @ 50/60 Hz DC Power Supply Rejection DC PSRR — -77 — dB AVDD and DVDD = 4.5 to 5.
MCP3901 SERIAL INTERFACE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all parameters apply: AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5V, -40°C < TA < +85°C, CLOAD = 30 pF Sym Min Typ Max Units Serial Clock Frequency Parameters fSCK — — — — 20 10 MHz MHz 4.5 ≤ DVDD ≤ 5.5 2.7 ≤ DVDD < 5.5 CS Setup Time tCSS 25 50 — — — — ns ns 4.5 ≤ DVDD ≤ 5.5 2.7 ≤ DVDD ≤ 5.5 CS Hold Time tCSH 50 100 — — — — ns ns 4.5 ≤ DVDD ≤ 5.5 2.7 ≤ DVDD < 5.
MCP3901 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5V Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 20L SSOP θJA — 89.
MCP3901 1/DRCLK DR tDRP tDODR SCK SDO FIGURE 1-3: Data Ready Pulse Timing Diagram. H Timing Waveform for tDIS Timing Waveform for tDO SCK VIH CS tDO 90% SDO SDO tDIS HI-Z 10% Timing Waveform for MDAT0/1 Modulator Output OSC1/CLKI tDOMDAT MDAT0/1 FIGURE 1-4: Specific Timing Diagrams.
MCP3901 2.0 TYPICAL PERFORMANCE CURVES Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 fIN = -0.5dBFS @ 60 Hz fD = 3.
MCP3901 Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. fIN = -0.5dBFS @ 60 Hz fD = 15.6 ksps 16384 Point FFT OSR = 64 Dithering ON 0 2000 4000 6000 120 110 100 90 80 70 60 50 40 30 20 10 0 Dithering ON Dithering OFF 32 8000 64 Spectral Response. Amplitude (dB) 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 fIN = -60dBFS @ 60 Hz fD = 15.
MCP3901 Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 14 95 90 85 80 75 70 65 60 55 50 45 40 OSR = 256 Frequency of Occurance SINAD (dB) Note: 12 OSR = 128 10 fIN = 60 Hz MCLK = 4 MHz OSR = 256 Dithering On 8 OSR = 64 6 OSR = 32 4 2 1 2 4 8 16 0 32 -105.0 -104.5 -104.0 -103.5 -103.0 -102.5 -102.
MCP3901 Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. fIN = 60 Hz MCLK = 4 MHz OSR = 64 Dithering OFF 1 0 8 6 4 0.6 G=8 0.5 Offset Error (mV) Frequency of Occurance 1 2 0.4 0.3 0.2 G=16 0.1 G=1 0 G=2 -0.1 2 G=32 G=4 -0.2 0 78.9 79 79.1 79.2 79.3 79.4 79.5 79.6 79.7 79.
MCP3901 Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 -2 G=1 G=2 G=8 G=16 G=4 G=32 -50 -25 0 25 50 75 100 125 Int. Voltage Reference (V) Positive Gain Error (% FS) Note: 2.37165 2.3716 2.37155 2.3715 2.37145 2.3714 2.37135 2.3713 4.5 150 4.8 Positive Gain Error vs. 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.
MCP3901 Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS @ 60 Hz. 100 80 60 40 20 0 -20 -40 -60 -80 -100 -0.5 2.5 OSR = 256 Dithering OFF SCK = 8 MHz 2 IDD (mA) INL (ppm) Note: Channel 0 Channel 1 1.5 1 DIDD 0.5 0 -0.25 0 0.25 0.5 Input Voltage (V) FIGURE 2-31: (Dithering Off). 0 1 2 3 4 5 6 MCLK (MHz) Integral Nonlinearity 50 FIGURE 2-33: Operating Current vs. Master Clock (MCLK).
MCP3901 3.0 PIN DESCRIPTION The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin No.
MCP3901 3.4 ADC Differential Analog inputs (CHn+/CHn-) CH0- and CH0+, and CH1- and CH1+, are the two fully differential analog voltage inputs for the Delta-Sigma ADCs. The linear and specified region of the channels are dependent on the PGA gain. This region corresponds to a differential voltage range of ±500 mV/GAIN with VREF = 2.4V. The maximum absolute voltage, with respect to AGND, for each CHn+/- input pin is ±1V with no distortion and ±6V with no breaking after continuous voltage. 3.
MCP3901 3.11 Oscillator and Master Clock Input Pins (OSC1/CLKI, OSC2) OSC1/CLKI and OSC2 provide the master clock for the device. When CLKEXT = 0 (default), a resonant crystal or clock source with a similar sinusoidal waveform must be placed across these pins to ensure proper operation. The typical clock frequency specified is 4 MHz. However, the clock frequency can be 1 MHz to 5 MHz without disturbing ADC accuracy. With the current boost circuit enabled, the master clock can be used up to 8.
MCP3901 NOTES: DS22192D-page 18 © 2011 Microchip Technology Inc.
MCP3901 4.0 TERMINOLOGY AND FORMULAS This section defines the terms and formulas used throughout this data sheet. The following terms are defined: MCLK – Master Clock AMCLK – Analog Master Clock 4.2 AMCLK – Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG1 PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two Sigma-Delta modulators.
MCP3901 Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. TABLE 4-2: PRE <1:0> The following table describes the various combinations of OSR and PRESCALE, and their associated AMCLK, DMCLK and DRCLK rates.
MCP3901 4.8 Integral Nonlinearity Error Integral nonlinearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. It is the maximum remaining error after calibration of offset and gain errors for a DC input signal. 4.
MCP3901 4.13 MCP3901 Delta-Sigma Architecture The MCP3901 incorporates two Delta-Sigma ADCs with a multi-bit architecture. A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which is digitizing the quantity of charge integrated by the modulator loop (see Figure 5-1). The quantizer is the block that is performing the Analog-to-Digital conversion.
MCP3901 4.16 Crosstalk The crosstalk is defined as the perturbation caused by one ADC channel on the other ADC channel. It is a measurement of the isolation between the two ADCs present in the chip. It is defined as: EQUATION 4-11: Δ V OUT PSRR ( dB ) = 20 log ⎛ -------------------⎞ ⎝ Δ AVDD⎠ This measurement is a two-step procedure: 1. 2. Measure one ADC input with no perturbation on the other ADC (ADC inputs shorted).
MCP3901 Each converter can be placed in Soft Reset mode independently. The Configuration registers are not modified by the Soft Reset mode. A data ready pulse will not be generated by any ADC while in Reset mode. Reset mode also effects the modulator output block (i.e., the MDAT pin, corresponding to the channel in Reset). If enabled, it provides a bitstream corresponding to a zero output (a series of ‘0011’ bits continuously repeated).
MCP3901 5.0 DEVICE OVERVIEW 5.3 5.1 Analog Inputs (CHn+/-) 5.3.1 The MCP3901 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or Rogowski coils). Each input pin is protected by specialized ESD structures that are certified to pass 7 kV HBM and 400V MM contact charge. These structures allow bipolar ±6V continuous voltage, with respect to AGND, to be present at their inputs without the risk of permanent damage.
MCP3901 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT For a specified voltage reference value of 2.4V, the modulators’ specified differential input range is ±500 mV. The input range is proportional to VREF and scales according to the VREF voltage. This range ensures the stability of the modulator over amplitude and frequency. Outside of this range, the modulator is still functional, however, its stability is no longer ensured, and therefore, it is not recommended to exceed this limit.
MCP3901 5.5 SINC3 Filter Both ADCs present in the MCP3901 include a decimation filter that is a third-order sinc (or notch) filter. This filter processes the multi-bit bitstream into 16 or 24-bit words (depending on the WIDTH Configuration bit). The settling time of the filter is 3 DMCLK periods. It is recommended that unsettled data be discarded to avoid data corruption, which can be done easily by setting the DR_LTY bit high in the STATUS/COM register.
MCP3901 5.6 ADC Output Coding The second-order modulator, SINC3 filter, PGA, VREF and analog input structure all work together to produce the device transfer function for the Analog-to-Digital conversion (see Equation 5-3). The channel data is either a 16-bit or 24-bit word, presented in a 23-bit or 15-bit plus sign, two’s complement format, and is MSB (left) justified. In case of positive saturation (CHn+ – CHn- > VREF/3), the output is locked to 7FFFFF for 24-bit mode (7FFF for 16-bit mode).
MCP3901 TABLE 5-6: OSR = 64 OUTPUT CODE EXAMPLES ADC Output code (MSB First) Hexadecimal Decimal 20-Bit Resolution 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0x7FFFF0 + 524, 287 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0x7FFFE0 + 524, 286 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0xFFFFF0 -1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0x800010 - 524,287 1 0 0 0 0 0 0 0 0 0 0 0 0 0
MCP3901 5.8 Power-on Reset 5.9 The MCP3901 contains an internal POR circuit that monitors analog supply voltage AVDD during operation. The typical threshold for a power-up event detection is 4.2V ±5%. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF ceramic and 10 µF tantalum) should be mounted as close as possible to the AVDD pin, providing additional transient immunity.
MCP3901 5.10.1 PHASE DELAY LIMITS 5.11 The phase delay can only go from -OSR/2 to +OSR/2 – 1. This sets the fine phase resolution. The PHASE register is coded with two’s complement. If larger delays between the two channels are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks. In this case, DRCLK would represent the coarse timing resolution, and DMCLK, the fine timing resolution.
MCP3901 NOTES: DS22192D-page 32 © 2011 Microchip Technology Inc.
MCP3901 6.0 6.1 SERIAL INTERFACE DESCRIPTION A5 A4 A3 A2 A1 A0 Overview The MCP3901 device is compatible with SPI Modes 0,0 and 1,1. Data is clocked out of the MCP3901 on the falling edge of SCK and data is clocked into the MCP3901 on the rising edge of SCK. In these modes, SCK can Idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent.
MCP3901 : CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI SDO A6 A5 A4 A3 A2 A1 A0 R/W HI-Z HI-Z D7 D6 D5 D4 D3 D2 D1 HI-Z D0 D7 D6 D5 D4 D3 D2 D1 (ADDRESS) DATA FIGURE 6-2: D0 (ADDRESS + 1) DATA Device Read (SPI Mode 1,1 – Clock Idles High).
MCP3901 6.6 SPI MODE 0,0 – Clock Idle Low, Read/Write Examples In this SPI mode, the clock Idles low. For the MCP3901, this means that there will be a rising edge before there is a falling edge.
MCP3901 6.7 Continuous Communication, Looping on Address Sets If the user wishes to read back either of the ADC channels continuously, or both channels continuously, the internal address counter of the MCP3901 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS returns high.
MCP3901 6.7.1 CONTINUOUS WRITE The following register sets are defined as types: Both ADCs are powered up with their default configurations, and begin to output DR pulses immediately (RESET<1:0> and SHUTDOWN<1:0> bits are off by default). TABLE 6-2: Type The default output codes for both ADCs are all zeros. The default modulator output for both ADCs is ‘0011’ (corresponding to a theoretical zero voltage at the inputs). The default phase is zero between the two channels.
MCP3901 6.9 Data Ready Pin (DR) To signify when channel data is ready for transmission, the data ready signal is available on the Data Ready pin (DR) through an active-low pulse at the end of a channel conversion. The data ready pin outputs an active-low pulse with a period that is equal to the DRCLK clock period, and with a width equal to one DMCLK period. When not active-low, this pin can either be in highimpedance (when DR_HIZN = 0) or in a defined logic high state (when DR_HIZN = 1).
MCP3901 The position of the DR pulses vary, with respect to this mode, to the OSR and to the PHASE settings: 6.10.2 • DRMODE<1:0> = 11: Both data ready pulses from ADC Channel 0 and ADC Channel 1 are output on the DR pin. • DRMODE<1:0> = 10: Data ready pulses from ADC Channel 1 are output on the DR pin. The DR from ADC Channel 0 is not present on the pin. • DRMODE<1:0> = 01: Data ready pulses from ADC Channel 0 are output on the DR pin. The DR from ADC Channel 1 is not present on the pin.
MCP3901 RESET RESET<0> or RESET<1> or SHUTDOWN<0> SHUTDOWN<1> DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR DRMODE=00; DR DRMODE=01; DR DRMODE=10; DR DRMODE=11; DR DRCLK Period 3*DRCLK period 1 DMCLK Period D6 DRCLK Period D5 D9 D4 D8 D16 D17 D3 D7 D14 D15 D2 D6 D12 D13 D6 D1 D5 D10 D11 D5 D6 D0 D4 D8 D9 D4 D5 D9 D7 D3 D7 D3 D4 D8 D6 D2 D6 D3 D7 D5 D1 D5 D6 D4 D0 D3 D4 D5 D3 D1
MCP3901 7.0 INTERNAL REGISTERS The addresses associated with the internal registers are listed below. A detailed description of the registers follows. All registers are 8-bit long and can be addressed separately. Read modes define the groups and types of registers for continuous read communication or looping on address sets. .
MCP3901 7.1 ADC Channel Data Output Registers The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with READ<1:0> bits). These registers are latched when an REGISTER 7-1: ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data is also latched to avoid data corruption issues.
MCP3901 7.2 Modulator Output Register The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on both ADCs. Each bit in this register corresponds to one comparator output on one of the channels. This register should be used as a read-only register. (Note 1). This register is updated at the refresh rate of DMCLK (typically, 1 MHz with MCLK = 4 MHz). See Section 5.4 “Modulator Output Block” for more details. .
MCP3901 7.3 7.3.1 PHASE Register PHASE RESOLUTION FROM OSR The PHASE register (PHASE<7:0>) is a 7 bits + sign, MSB first, two’s complement register that indicates how much phase delay there should be between Channel 0 and Channel 1. The timing resolution of the phase delay is 1/DMCLK, or 1 µs, in the default configuration (MCLK = 4 MHz).
MCP3901 7.4 Gain Configuration Register This register contains the settings for the PGA gains for each channel as well as the BOOST options for each channel.
MCP3901 7.5 Status and Communication Register This register contains all settings related to the communication, including data ready settings and status, and Read mode settings. 7.5.1 DATA READY (DR) LATENCY CONTROL – DR_LTY This bit determines if the first data ready pulses correspond to settled data or unsettled data from each SINC3 filter. Unsettled data will provide DR pulses every DRCLK period.
MCP3901 REGISTER 7-5: R/W-1 STATUS AND COMMUNICATION REGISTER: ADDRESS 0x09 R/W-0 READ<1> READ<0> R/W-1 R/W-0 DR_LTY DR_HIZN R/W-0 R/W-0 R-1 R-1 DRMODE<1> DRMODE<0> DRSTATUS_CH1 DRSTATUS_CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 READ<1:0>: Address Loop Setting bits 11 = Address counter loops on entire register map 10 = Address counter loops on register
MCP3901 7.6 Configuration Registers The Configuration registers contain settings for the internal clock prescaler, the oversampling ratio, the Channel 0 and Channel 1 width settings of 16 or REGISTER 7-6: 24 bits, the modulator output control settings, the state of the channel Resets and shutdowns, the dithering algorithm control (for Idle tones suppression), and the control bits for the external VREF and external CLK.
MCP3901 REGISTER 7-6: CONFIGURATION REGISTERS: CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B (CONTINUED) bit 1 VREFEXT: Internal Voltage Reference Shutdown Control bit 1 = Internal voltage reference disabled, an external voltage reference must be placed between REFIN+/OUT and REFIN0 = Internal voltage reference enabled (default) bit 0 CLKEXT: Clock Mode bit 1 = External Clock mode (internal oscillator disabled and bypassed – lower power) 0 = XT mode – A crystal must be placed between OSC1/OSC2 (default)
MCP3901 NOTES: DS22192D-page 50 © 2011 Microchip Technology Inc.
MCP3901 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 20-Lead SSOP (SS) XXXXXXXX XXXXXXXX YYWWNNN 20-Lead QFN Example: MCP3901A0 e3 E/SS^^ 1049256 MCP3901A0 e3 I/SS^^ 1049256 Examples: XXXXXXX 39010 39010 XXXXXXX I/ML e3 E/ML e3 YYWWNNN 1049256 1049256 Legend: XX...
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MCP3901 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc.
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MCP3901 NOTES: DS22192D-page 56 © 2011 Microchip Technology Inc.
MCP3901 APPENDIX A: REVISION HISTORY Revision D (April 2011) The following is the list of modifications: 1. 2. Added the 20-lead QFN package and related information throughout the document. Added the E Temperature package option. Revision C (August 2010) The following is the list of modifications: 1. 2. Corrected symbols inside the Functional Block Diagram figure. Typographical revisions throughout document. Revision B (November 2009) The following is the list of modifications: 1.
MCP3901 NOTES: DS22192D-page 58 © 2011 Microchip Technology Inc.
MCP3901 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. XX Device Address Options Device: X X Tape and Temperature Reel Range MCP3901: Address Options: XX /XX Package Two-Channel ΔΣ A/D Converter A6 A5 A0* = 0 0 A1 = 0 1 A2 = 1 0 A3 = 1 1 Examples: a) MCP3901A0-I/SS: b) MCP3901A0T-I/SS: c) MCP3901A1-I/SS: d) MCP3901A1T-I/SS: e) MCP3901A0-E/ML: * Default option.
MCP3901 NOTES: DS22192D-page 60 © 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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