Datasheet
MCP3901
DS22192D-page 6 © 2011 Microchip Technology Inc.
SERIAL INTERFACE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply: AV
DD
= 4.5 to 5.5V, DV
DD
= 2.7 to 5.5V,
-40°C < T
A
< +85°C, C
LOAD
= 30 pF
Parameters Sym Min Typ Max Units Conditions
Serial Clock Frequency f
SCK
—
—
—
—
20
10
MHz
MHz
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
< 5.5
CS
Setup Time t
CSS
25
50
—
—
—
—
ns
ns
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
≤ 5.5
CS
Hold Time
t
CSH
50
100
—
—
—
—
ns
ns
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
< 5.5
CS
Disable Time t
CSD
50 — — ns
Data Setup Time t
SU
5
10
—
—
—
—
ns
ns
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
< 5.5
Data Hold Time t
HD
10
20
—
—
—
—
ns
ns
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
< 5.5
Serial Clock High Time t
HI
20
50
—
—
—
—
ns
ns
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
< 5.5
Serial Clock Low Time t
LO
20
50
—
—
—
—
ns
ns
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
< 5.5
Serial Clock Delay Time t
CLD
50 — — ns
Serial Clock Enable Time t
CLE
50 — — ns
Output Valid from SCK Low t
DO
— — 50 ns 2.7 ≤ DV
DD
< 5.5
Modulator Output Valid from AMCLK
High
t
DOMDAT
— — 1/2 * AMCLK s
Output Hold Time t
HO
0——ns(Note 1)
Output Disable Time t
DIS
—
—
—
—
25
50
ns
ns
4.5 ≤ DV
DD
≤ 5.5
2.7 ≤ DV
DD
< 5.5 (Note 1)
Reset Pulse Width (RESET
)t
MCLR
100 — — ns 2.7 ≤ DV
DD
< 5.5
Data Transfer Time to DR
(data ready) t
DODR
— — 50 ns 2.7 ≤ DV
DD
< 5.5
Data Ready Pulse Low Time t
DRP
—1/DMCLK — µs2.7 ≤ DV
DD
< 5.5
Schmitt Trigger High-Level Input Voltage V
IH1
.7 DV
DD
—DV
DD
+ 1 V
Schmitt Trigger Low-Level Input Voltage V
IL1
-0.3 — 0.2 DV
DD
V
Hysteresis of Schmitt Trigger Inputs
(all digital inputs)
V
HYS
300 — — mV
Low-Level Output Voltage, SDO Pin V
OL
— — 0.4 V SDO pin only,
I
OL
= +2.0 mA, V
DD
= 5.0V
Low-level output voltage, DR
and
MDAT Pins
V
OL
——0.4VDR and MDAT pins only,
I
OL
= +800 mA, V
DD
= 5.0V
High-level output voltage, SDO pin V
OH
DV
DD
– 0.5 — — V SDO pin only,
I
OH
= -2.0 mA, V
DD
= 5.0V
High-level output voltage, DR
and
MDAT pins
V
OH
DV
DD
– 0.5 — — V DR and MDAT pins only,
I
OH
= -800 µA, V
DD
= 5.0V
Input leakage current I
LI
—— ±1µACS = DV
DD
,
V
IN
= DGND or DV
DD
Output leakage current I
LO
—— ±1µACS = DV
DD
,
V
OUT
= DGND or DV
DD
Internal capacitance (all inputs and
outputs)
C
INT
—— 7pFT
A
= 25°C,
SCK = 1.0 MHz,
DV
DD
= 5.0V (Note 1)
Note 1: This parameter is periodically sampled and not 100% tested.