Datasheet

© 2011 Microchip Technology Inc. DS22192D-page 39
MCP3901
The position of the DR pulses vary, with respect to this
mode, to the OSR and to the PHASE settings:
DRMODE<1:0> = 11: Both data ready pulses
from ADC Channel 0 and ADC Channel 1 are
output on the DR
pin.
DRMODE<1:0> = 10: Data ready pulses from
ADC Channel 1 are output on the DR
pin. The DR
from ADC Channel 0 is not present on the pin.
DRMODE<1:0> = 01: Data ready pulses from
ADC Channel 0 are output on the DR
pin. The DR
from ADC Channel 1 is not present on the pin.
DRMODE<1:0> = 00 (Recommended and
Default mode): Data ready pulses from the
lagging ADC between the two are output on the
DR
pin. The lagging ADC depends on the PHASE
register and on the OSR. In this mode, the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready.
6.10.2 DR PULSES WITH SHUTDOWN OR
RESET CONDITIONS
There will be no DR pulses if DRMODE<1:0> = 00
when either one or both of the ADCs are in Reset or
shutdown. In Mode 0,0, a DR
pulse only happens when
both ADCs are ready. Any DR
pulse will correspond to
one data on both ADCs. The two ADCs are linked
together and act as if there was only one channel with
the combined data of both ADCs. This mode is very
practical when both ADC channels’ data retrieval and
processing need to be synchronized, as in power
metering applications.
Figure 6-8 represents the behavior of the data ready
pin with the different DRMODE and DR_LTY
configurations, while shutdown or Resets are applied.
Note: If DRMODE<1:0> = 11, the user will still
be able to retrieve the DR
pulse for the
ADC not in shutdown or Reset (i.e., only
1 ADC channel needs to be awake).