Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: INL Error vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-2: INL Error vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-3: INL Error vs. Input Voltage (VDD = 5.0V, VREF = 5V).
- FIGURE 2-4: Maximum INL Error vs. VREF.
- FIGURE 2-5: Maximum INL Error vs. Temperature.
- FIGURE 2-6: Output Noise vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-7: Output Noise vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-8: Output Noise vs. VREF.
- FIGURE 2-9: Output Noise vs.VDD.
- FIGURE 2-10: Output Noise vs. Temperature.
- FIGURE 2-11: Offset Error vs VDD (VCM = 0V).
- FIGURE 2-12: Offset Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-13: Full Scale Error vs. VDD.
- FIGURE 2-14: Full Scale Error vs. Temperature.
- FIGURE 2-15: Full Scale Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-16: MCP3550/1 Output Noise Histogram.
- FIGURE 2-17: MCP3553 Output Noise Histogram.
- FIGURE 2-18: Total Unadjusted Error (TUE) vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-19: Total Unadjusted Error (TUE) vs. Input Voltage.
- FIGURE 2-20: Total Unadjusted Error (TUE) vs. Input Voltage (VREF = 5.0V).
- FIGURE 2-21: Maximum TUE vs. VREF.
- FIGURE 2-22: Maximum TUE vs. Temperature.
- FIGURE 2-23: Maximum TUE vs. VDD.
- FIGURE 2-24: IDDS vs. Temperature.
- FIGURE 2-25: IDD vs. VDD.
- FIGURE 2-26: IDD vs. Temperature.
- 3.0 Pin Descriptions
- 4.0 Device Overview
- FIGURE 4-1: MCP3550/1/3 Functional Block Diagram.
- 4.1 MCP3550/1/3 Delta-Sigma Modulator with Internal Offset and Gain Calibration
- 4.2 Digital Filter
- TABLE 4-1: data rate, output noise and Digital filter specificaTIons by device
- FIGURE 4-2: SINC Filter Response, MCP3550-50 Device.
- FIGURE 4-3: SINC Filter Response, MCP3550-60 Device.
- FIGURE 4-4: SINC Filter Response, MCP3551 Device, Simultaneous 50/60 Hz Rejection.
- FIGURE 4-5: SINC Filter Response at Integer Multiples of the Sampling Frequency (fs).
- 4.3 Internal Oscillator
- 4.4 Differential Analog Inputs
- 4.5 Voltage Reference Input Pin
- 4.6 Power-On Reset (POR)
- 4.7 Shutdown Mode
- 4.8 Sleep Mode
- 5.0 Serial Interface
- 6.0 Packaging Information
© 2009 Microchip Technology Inc. DS21950E-page 25
MCP3550/1/3
5.5 Using The MCP3550/1/3 with
Microcontroller (MCU) SPI Ports
It is required that the microcontroller SPI port be
configured to clock out data on the falling edge of clock
and latch data in on the rising edge. Figure 5-6 depicts
the operation shown in SPI mode 1,1, which requires
that the SCK from the MCU idles in the High state,
while Figure 5-7 shows the similar case of SPI Mode
0,0, where the clock idles in the Low state. The
waveforms in the figures are examples of an MCU
operating the SPI port in 8-bit mode, and the
MCP3550/1/3 devices do not require data in 8-bit
groups.
In SPI mode 1,1, data is read using only 24 clocks or
three byte transfers. The data ready bit must be read
by testing the SDO/RDY
line prior to a falling edge of
the clock.
In SPI mode 0,0, data is read using 25 clocks or four
byte transfers. Please note that the data ready bit is
included in the transfer as the first bit in this mode.
FIGURE 5-6: SPI Communication – Mode 1,1.
FIGURE 5-7: SPI Communication – Mode 0,0.
CS
SCK
SDO/RDY
MCU
Data stored into MCU
receive register after
transmission of first byte
Receive
Buffer
Data stored into MCU
receive register after
transmission of second byte
Data stored into MCU
receive register after
transmission of third byte
DOO
21
20 19 18 17
16
15 14 13 12 11 10 9
8
76543 21 0
OL OH 21 20 19 18 17 16
15 14 13 12 11 10 9 8
76543210
RHL
CS
SCK
SDO/RDY
MCU
Data stored into MCU
receive register after
transmission of first byte
Receive
Buffer
Data stored into MCU
receive register after
transmission of second byte
Data stored into MCU
receive register after
transmission of third byte
Data stored into MCU
receive register after
transmission of fourth byte
DR
OO
21 20 19 18 17
16 14 13 12 11 10 9
65432
0
OH OL 21 20 19 18 17
15 14 13 12 11 10 9
7654321 0
DR
8
16
15
7
8
1
HL