Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: INL Error vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-2: INL Error vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-3: INL Error vs. Input Voltage (VDD = 5.0V, VREF = 5V).
- FIGURE 2-4: Maximum INL Error vs. VREF.
- FIGURE 2-5: Maximum INL Error vs. Temperature.
- FIGURE 2-6: Output Noise vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-7: Output Noise vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-8: Output Noise vs. VREF.
- FIGURE 2-9: Output Noise vs.VDD.
- FIGURE 2-10: Output Noise vs. Temperature.
- FIGURE 2-11: Offset Error vs VDD (VCM = 0V).
- FIGURE 2-12: Offset Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-13: Full Scale Error vs. VDD.
- FIGURE 2-14: Full Scale Error vs. Temperature.
- FIGURE 2-15: Full Scale Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-16: MCP3550/1 Output Noise Histogram.
- FIGURE 2-17: MCP3553 Output Noise Histogram.
- FIGURE 2-18: Total Unadjusted Error (TUE) vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-19: Total Unadjusted Error (TUE) vs. Input Voltage.
- FIGURE 2-20: Total Unadjusted Error (TUE) vs. Input Voltage (VREF = 5.0V).
- FIGURE 2-21: Maximum TUE vs. VREF.
- FIGURE 2-22: Maximum TUE vs. Temperature.
- FIGURE 2-23: Maximum TUE vs. VDD.
- FIGURE 2-24: IDDS vs. Temperature.
- FIGURE 2-25: IDD vs. VDD.
- FIGURE 2-26: IDD vs. Temperature.
- 3.0 Pin Descriptions
- 4.0 Device Overview
- FIGURE 4-1: MCP3550/1/3 Functional Block Diagram.
- 4.1 MCP3550/1/3 Delta-Sigma Modulator with Internal Offset and Gain Calibration
- 4.2 Digital Filter
- TABLE 4-1: data rate, output noise and Digital filter specificaTIons by device
- FIGURE 4-2: SINC Filter Response, MCP3550-50 Device.
- FIGURE 4-3: SINC Filter Response, MCP3550-60 Device.
- FIGURE 4-4: SINC Filter Response, MCP3551 Device, Simultaneous 50/60 Hz Rejection.
- FIGURE 4-5: SINC Filter Response at Integer Multiples of the Sampling Frequency (fs).
- 4.3 Internal Oscillator
- 4.4 Differential Analog Inputs
- 4.5 Voltage Reference Input Pin
- 4.6 Power-On Reset (POR)
- 4.7 Shutdown Mode
- 4.8 Sleep Mode
- 5.0 Serial Interface
- 6.0 Packaging Information
MCP3550/1/3
DS21950E-page 22 © 2009 Microchip Technology Inc.
5.2 Controlling Internal Conversions
and the Internal Oscillator
During Shutdown mode, on the falling edge of CS, the
conversion process begins. During this process, the
internal oscillator clocks the delta-sigma modulator and
the SINC filter until a conversion is complete. This
conversion time is t
CONV
and the timing is shown in
Figure 5-2. At the end of t
CONV
, the digital filter has
settled completely and there is no latency involved with
the digital SINC filter of the MCP3550/1/3.
The two modes of conversion for the MCP3550/1/3
devices are Single Conversion and Continuous
Conversion. In Single Conversion mode, a consecutive
conversion will not automatically begin. Instead, after a
single conversion is complete and the SINC filter have
settled, the device puts the data into the output register
and enters shutdown.
In Continuous Conversion mode, a consecutive
conversion will be automatic. In this mode, the device
is continuously converting, independent of the serial
interface. The most recent conversion data will always
be available in the Output register.
When the device exits Shutdown, there is an internal
power-up delay that must be observed.
FIGURE 5-2: Single Conversion Mode.
FIGURE 5-3: Continuous Conversion Mode.
CS
Int. Osc
t
CONV
Sleep
Shutdown
SCK (opt)
SDO/RDY
Hi-Z
Hi-Z
x24
CS
Int. Osc
t
CONV
Shutdown
SCK (opt)
t
CONV
t
CONV
SDO/RDY
Hi-Z
x24