Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: INL Error vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-2: INL Error vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-3: INL Error vs. Input Voltage (VDD = 5.0V, VREF = 5V).
- FIGURE 2-4: Maximum INL Error vs. VREF.
- FIGURE 2-5: Maximum INL Error vs. Temperature.
- FIGURE 2-6: Output Noise vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-7: Output Noise vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-8: Output Noise vs. VREF.
- FIGURE 2-9: Output Noise vs.VDD.
- FIGURE 2-10: Output Noise vs. Temperature.
- FIGURE 2-11: Offset Error vs VDD (VCM = 0V).
- FIGURE 2-12: Offset Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-13: Full Scale Error vs. VDD.
- FIGURE 2-14: Full Scale Error vs. Temperature.
- FIGURE 2-15: Full Scale Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-16: MCP3550/1 Output Noise Histogram.
- FIGURE 2-17: MCP3553 Output Noise Histogram.
- FIGURE 2-18: Total Unadjusted Error (TUE) vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-19: Total Unadjusted Error (TUE) vs. Input Voltage.
- FIGURE 2-20: Total Unadjusted Error (TUE) vs. Input Voltage (VREF = 5.0V).
- FIGURE 2-21: Maximum TUE vs. VREF.
- FIGURE 2-22: Maximum TUE vs. Temperature.
- FIGURE 2-23: Maximum TUE vs. VDD.
- FIGURE 2-24: IDDS vs. Temperature.
- FIGURE 2-25: IDD vs. VDD.
- FIGURE 2-26: IDD vs. Temperature.
- 3.0 Pin Descriptions
- 4.0 Device Overview
- FIGURE 4-1: MCP3550/1/3 Functional Block Diagram.
- 4.1 MCP3550/1/3 Delta-Sigma Modulator with Internal Offset and Gain Calibration
- 4.2 Digital Filter
- TABLE 4-1: data rate, output noise and Digital filter specificaTIons by device
- FIGURE 4-2: SINC Filter Response, MCP3550-50 Device.
- FIGURE 4-3: SINC Filter Response, MCP3550-60 Device.
- FIGURE 4-4: SINC Filter Response, MCP3551 Device, Simultaneous 50/60 Hz Rejection.
- FIGURE 4-5: SINC Filter Response at Integer Multiples of the Sampling Frequency (fs).
- 4.3 Internal Oscillator
- 4.4 Differential Analog Inputs
- 4.5 Voltage Reference Input Pin
- 4.6 Power-On Reset (POR)
- 4.7 Shutdown Mode
- 4.8 Sleep Mode
- 5.0 Serial Interface
- 6.0 Packaging Information
© 2009 Microchip Technology Inc. DS21950E-page 5
MCP3550/1/3
Voltage Output Low (SDO/RDY)V
OL
——0.4 VV
OH
= -1 mA, V
DD
= 5.0V
Input leakage Current
(CS
, SCK)
I
LI
-1 — 1 µA
Internal Pin Capacitance
(CS
, SCK, SDO/RDY)
C
INT
—5— pFNote 1
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ T
A
≤ +85°C, V
DD
= 2.7V or 5.0V.
V
REF
= 2.5V. V
IN
+ = V
IN
- = V
CM
= V
REF
/2. All ppm units use 2*V
REF
as full scale range. Unless otherwise noted, specification
applies to entire MCP3550/1/3 family.
Parameters Sym Min Typ Max Units Conditions
Note 1: This parameter is established by characterization and not 100% tested.
2: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
3: This current is due to the leakage current and the current due to the offset voltage between V
IN
+ and V
IN
-.
4: Input impedance is inversely proportional to clock frequency; typical values are for the MCP3550/1 device. V
REF
=5V.
5: Characterized by design, but not tested.
6: Rejection performance depends on internal oscillator accuracy; see Section 4.0 “Device Overview” for more informa-
tion on oscillator and digital filter design. MCP3550/1 device rejection specifications characterized from 49 to 61 Hz.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range T
A
-40 — +85 °C
Operating Temperature Range T
A
-40 — +125 °C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP θ
JA
—211—°C/W
Thermal Resistance, 8L-SOIC θ
JA
— 149.5 — °C/W
SERIAL TIMINGS
Electrical Specifications: Unless otherwise indicated, all parameters apply at -40°C ≤ T
A
≤ +85°C,
V
DD
= 3.3V or 5.0V, SDO load = 50 pF.
Parameters Sym Min Typ Max Units Conditions
CLK Frequency f
SCK
—— 5MHz
CLK High t
HI
90 — — ns
CLK Low t
LO
90 — — ns
CLK fall to output data valid t
DO
0—90ns
CS
low to indicate RDY state t
RDY
0—50ns
CS
minimum low time t
CSL
50 — — ns
RDY
flag setup time t
SU
20 — — ns
CS
rise to output disable t
DIS
20 — — ns
CS
disable time t
CSD
90 — — ns
Power-up to CS
LOW t
PUCSL
—10—µs
CS
High to Shutdown Mode t
CSHSD
—10—µs