Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: INL Error vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-2: INL Error vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-3: INL Error vs. Input Voltage (VDD = 5.0V, VREF = 5V).
- FIGURE 2-4: Maximum INL Error vs. VREF.
- FIGURE 2-5: Maximum INL Error vs. Temperature.
- FIGURE 2-6: Output Noise vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-7: Output Noise vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-8: Output Noise vs. VREF.
- FIGURE 2-9: Output Noise vs.VDD.
- FIGURE 2-10: Output Noise vs. Temperature.
- FIGURE 2-11: Offset Error vs VDD (VCM = 0V).
- FIGURE 2-12: Offset Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-13: Full Scale Error vs. VDD.
- FIGURE 2-14: Full Scale Error vs. Temperature.
- FIGURE 2-15: Full Scale Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-16: MCP3550/1 Output Noise Histogram.
- FIGURE 2-17: MCP3553 Output Noise Histogram.
- FIGURE 2-18: Total Unadjusted Error (TUE) vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-19: Total Unadjusted Error (TUE) vs. Input Voltage.
- FIGURE 2-20: Total Unadjusted Error (TUE) vs. Input Voltage (VREF = 5.0V).
- FIGURE 2-21: Maximum TUE vs. VREF.
- FIGURE 2-22: Maximum TUE vs. Temperature.
- FIGURE 2-23: Maximum TUE vs. VDD.
- FIGURE 2-24: IDDS vs. Temperature.
- FIGURE 2-25: IDD vs. VDD.
- FIGURE 2-26: IDD vs. Temperature.
- 3.0 Pin Descriptions
- 4.0 Device Overview
- FIGURE 4-1: MCP3550/1/3 Functional Block Diagram.
- 4.1 MCP3550/1/3 Delta-Sigma Modulator with Internal Offset and Gain Calibration
- 4.2 Digital Filter
- TABLE 4-1: data rate, output noise and Digital filter specificaTIons by device
- FIGURE 4-2: SINC Filter Response, MCP3550-50 Device.
- FIGURE 4-3: SINC Filter Response, MCP3550-60 Device.
- FIGURE 4-4: SINC Filter Response, MCP3551 Device, Simultaneous 50/60 Hz Rejection.
- FIGURE 4-5: SINC Filter Response at Integer Multiples of the Sampling Frequency (fs).
- 4.3 Internal Oscillator
- 4.4 Differential Analog Inputs
- 4.5 Voltage Reference Input Pin
- 4.6 Power-On Reset (POR)
- 4.7 Shutdown Mode
- 4.8 Sleep Mode
- 5.0 Serial Interface
- 6.0 Packaging Information
MCP3550/1/3
DS21950E-page 24 © 2009 Microchip Technology Inc.
5.4.1 READY FUNCTION OF SDO/RDY
PIN IN CONTINUOUS CONVERSION
MODE
The device enters Continuous Conversion mode if no
rising edge of CS
is seen during t
CONV
and
consecutive conversions ensue. SDO/RDY will be
high, indicating that a conversion is in process. When
a conversion is complete, SDO/RDY
will change to a
Low state. With the Low state of SDO/RDY after this
first conversion, the conversion data can be accessed
with the combination of SCK and SDO/RDY
. If the data
ready event happens during the clocking out of the
data, the data ready bit will be displayed after the
complete 24-bit word communication (i.e., the data
ready event will not interrupt a data transfer).
If 24 bits of data are required from this conversion, they
must be accessed during this communication. You can
terminate data transition by bringing CS
high, but the
remaining data will be lost and the converter will go into
Shutdown mode. Once the data has been transmitted
by the converter, the SDO/RDY
pin will remain in the
LSB state until the 25th falling edge of SCK. At this
point, SDO/RDY
is released from the Data Acquisition
mode and changed to the RDY state.
5.4.2 2-WIRE CONTINUOUS
CONVERSION OPERATION,
(CS
TIED PERMANENTLY LOW)
It is possible to use only two wires to communicate with
the MCP3550/1/3 devices. In this state, the device is
always in Continuous Conversion mode, with internal
conversions continuously occurring. This mode can be
entered by having CS
low during power-up or changing
it to a low position after power-up. If CS is low at power-
up, the first conversion of the converter is initiated
approximately 300 µs after the power supply has
stabilized.
Note: The RDY state is not latched to CS in this
mode; the RDY flag dynamically updates
on the SDO/RDY
pin and remains in this
state until data is clocked out using the
SCK pin.