Datasheet
Table Of Contents
- 1.0 Electrical Characteristics
- 2.0 Typical Performance Curves
- FIGURE 2-1: INL Error vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-2: INL Error vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-3: INL Error vs. Input Voltage (VDD = 5.0V, VREF = 5V).
- FIGURE 2-4: Maximum INL Error vs. VREF.
- FIGURE 2-5: Maximum INL Error vs. Temperature.
- FIGURE 2-6: Output Noise vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-7: Output Noise vs. Input Voltage (VDD = 5.0V).
- FIGURE 2-8: Output Noise vs. VREF.
- FIGURE 2-9: Output Noise vs.VDD.
- FIGURE 2-10: Output Noise vs. Temperature.
- FIGURE 2-11: Offset Error vs VDD (VCM = 0V).
- FIGURE 2-12: Offset Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-13: Full Scale Error vs. VDD.
- FIGURE 2-14: Full Scale Error vs. Temperature.
- FIGURE 2-15: Full Scale Error vs. Temperature (VREF = 5.0V).
- FIGURE 2-16: MCP3550/1 Output Noise Histogram.
- FIGURE 2-17: MCP3553 Output Noise Histogram.
- FIGURE 2-18: Total Unadjusted Error (TUE) vs. Input Voltage (VDD = 2.7V).
- FIGURE 2-19: Total Unadjusted Error (TUE) vs. Input Voltage.
- FIGURE 2-20: Total Unadjusted Error (TUE) vs. Input Voltage (VREF = 5.0V).
- FIGURE 2-21: Maximum TUE vs. VREF.
- FIGURE 2-22: Maximum TUE vs. Temperature.
- FIGURE 2-23: Maximum TUE vs. VDD.
- FIGURE 2-24: IDDS vs. Temperature.
- FIGURE 2-25: IDD vs. VDD.
- FIGURE 2-26: IDD vs. Temperature.
- 3.0 Pin Descriptions
- 4.0 Device Overview
- FIGURE 4-1: MCP3550/1/3 Functional Block Diagram.
- 4.1 MCP3550/1/3 Delta-Sigma Modulator with Internal Offset and Gain Calibration
- 4.2 Digital Filter
- TABLE 4-1: data rate, output noise and Digital filter specificaTIons by device
- FIGURE 4-2: SINC Filter Response, MCP3550-50 Device.
- FIGURE 4-3: SINC Filter Response, MCP3550-60 Device.
- FIGURE 4-4: SINC Filter Response, MCP3551 Device, Simultaneous 50/60 Hz Rejection.
- FIGURE 4-5: SINC Filter Response at Integer Multiples of the Sampling Frequency (fs).
- 4.3 Internal Oscillator
- 4.4 Differential Analog Inputs
- 4.5 Voltage Reference Input Pin
- 4.6 Power-On Reset (POR)
- 4.7 Shutdown Mode
- 4.8 Sleep Mode
- 5.0 Serial Interface
- 6.0 Packaging Information
MCP3550/1/3
DS21950E-page 16 © 2009 Microchip Technology Inc.
4.1 MCP3550/1/3 Delta-Sigma
Modulator with Internal Offset and
Gain Calibration
The converter core of the MCP3550/1/3 devices is a
third-order delta-sigma modulator with automatic gain
and offset error calibrations. The modulator uses a 1-bit
DAC structure. The delta-sigma modulator processes
the sampled charges through switched capacitor
structures controlled by a very low drift oscillator for
reduced clock jitter.
During the conversion process, the modulator outputs
a bit stream with the bit frequency equivalent to the
f
OSC
/4 (see Tabl e 4-1). The high oversampling
implemented in the modulator ensures very high
resolution and high averaging factor to achieve low-
noise specifications. The bit stream output of the
modulator is then processed by the digital decimation
filter in order to provide a 22-bit output code at a data
rate of 12.5 Hz for the MCP3550-50, 15 Hz for the
MCP3550-60, 13.75 Hz for the MCP3551 and 60 Hz
for the MCP3553. Since the oversampling ratio is lower
with the MCP3553 device, a much higher output data
rate is achieved while still achieving 20 bits No Missing
Codes (NMC) and 20.6 ENOB.
A self-calibration of offset and gain occurs at the onset
of every conversion. The conversion data available at
the output of the device is always calibrated for offset
and gain through this process. This offset and gain
auto-calibration is performed internally and has no
impact on the speed of the converter since the offset
and gain errors are calibrated in real-time during the
conversion. The real-time offset and gain calibration
schemes do not affect the conversion process.
4.2 Digital Filter
The MCP3550/1/3 devices include a digital decimation
filter, which is a fourth-order modified SINC filter. This
filter averages the incoming bit stream from the
modulator and outputs a 22-bit conversion word in
binary two's complement. When all bits have been
processed by the filter, the output code is ready for SPI
communication, the RDY
flag is set on the SDO/RDY
pin and all the internal registers are reset in order to
process the next conversion.
Like the commonly used SINC filter, the modified SINC
filter in the MCP3550/1/3 family has the main notch
frequency located at f
S
/(OSR*L), where f
S
is the bit
stream sample frequency. OSR is the Oversampling
Ratio and L is the order of the filter.
The MCP3550-50 device has the main filter notch
located at 50 Hz. For the MCP3550-60 device, the
notch is located at 60 Hz. The MCP3551 device has its
notch located at 55 Hz, and for the MCP3553 device,
the main notch is located at 240 Hz, with an OSR of
128. (see Table 4-1 for rejection performance).
The digital decimation SINC filter has been modified in
order to offer staggered zeros in its transfer function.
This modification is intended to widen the main notch in
order to be less sensitive to oscillator deviation or line-
frequency drift. The MCP3551 filter has staggered
zeros spread in order to reject both 50 Hz and 60 Hz
line frequencies simultaneously (see Figure 4-2).
TABLE 4-1: DATA RATE, OUTPUT NOISE AND DIGITAL FILTER SPECIFICATIONS BY DEVICE
Device
Output Data
Rate (t
CONV
)
(Note)
Output
Noise
(µV
RMS
)
Primary
Notch
(Hz)
Sample
Frequency
(f
S
)
Internal
Clock
f
OSC
50/60 Hz Rejection
MCP3550-50 80.00 ms 2.5 50 25600 Hz 102.4 kHz -120 dB min. at
50 Hz
MCP3550-60 66.67 ms 2.5 60 30720 Hz 122.88 kHz -120 dB min. at
60 Hz
MCP3551 72.73 ms 2.5 55 28160 Hz 112.64 kHz -82 dB min. from
48 Hz to 63 Hz. -
82 dB at 50 Hz and
-88 dB at 60 Hz
MCP3553 16.67 ms 6 240 30720 Hz 122.88 kHz Not Applicable
Note: For the first conversion after exiting Shutdown, t
CONV
must include an additional 144 f
OSC
periods before
the conversion is complete and the RDY
(Ready) flag appears on SDO/RDY.