Datasheet

MCP3302/04
DS21697F-page 4  2011 Microchip Technology Inc.
Analog Inputs
Full Scale Input Span CH0 - CH7 -V
REF
—V
REF
V
Absolute Input Voltage CH0 - CH7 -0.3 — V
DD
+ 0.3 V
Leakage Current — 0.001 ±1 µA
Switch Resistance R
S
—1 — kΩ See Figure 5-3
Sample Capacitor C
SAMPLE
— 25 — pF See Figure 5-3
Digital Input/Output
Data Coding Format Binary Two’s Complement
High Level Input Voltage V
IH
0.7 V
DD
—— V
Low Level Input Voltage V
IL
— — 0.3 V
DD
V
High Level Output Voltage V
OH
4.1 — — V I
OH
= -1 mA, V
DD
= 4.5V
Low Level Output Voltage V
OL
—— 0.4 VI
OL
= 1 mA, V
DD
= 4.5V
Input Leakage Current I
LI
-10 — 10 µA V
IN
= V
SS
or V
DD
Output Leakage Current I
LO
-10 — 10 µA V
OUT
= V
SS
or V
DD
Pin Capacitance C
IN
, C
OUT
— — 10 pF T
A
= +25°C, F = 1 MHz, Note 1
Timing Specifications:
Clock Frequency (Note 8) F
CLK
0.105 — 2.1 MHz V
DD
= 5V, F
SAMPLE
= 100 ksps
Clock High Time T
HI
210 — — ns Note 5
Clock Low Time T
LO
210 — — ns Note 5
CS
Fall To First Rising CLK Edge T
SUCS
100 — — ns
Data In Setup time T
SU
50 — — ns
Data In Hold Time T
HD
50 — — ns
CLK Fall To Output Data Valid T
DO
—— 125 nsV
DD
= 5V, see Figure 1-2
— — 200 ns V
DD
= 2.7V, see Figure 1-2
CLK Fall To Output Enable T
EN
—— 125 nsV
DD
= 5V, see Figure 1-2
— — 200 ns V
DD
= 2.7V, see Figure 1-2
CS
Rise To Output Disable T
DIS
— — 100 ns See test circuits, Figure 1-2
Note 1
CS
Disable Time T
CSH
475 — — ns
D
OUT
Rise Time T
R
— — 100 ns See test circuits, Figure 1-2
Note 1
D
OUT
Fall Time T
F
— — 100 ns See test circuits, Figure 1-2
Note 1
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, all parameters apply at V
DD
= 5V, V
SS
= 0V, and V
REF
= 5V. Full differential
input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with
T
A
= -40°C to +85°C (Note 7). Conversion speed (F
SAMPLE
) is 100 ksps with F
CLK
= 21*F
SAMPLE
Parameter Symbol Min Typ Max Units Conditions
Note 1: This specification is established by characterization and not 100% tested.
2: See characterization graphs that relate converter performance to V
REF
level.
3: V
IN
= 0.1V to 4.9V @ 1 kHz.
4: V
DD
=5V DC ±500 mV
P-P
@ 1 kHz, see test circuit Figure 1-4.
5: Maximum clock frequency specification must be met.
6: V
REF
= 400 mV, V
IN
= 0.1V to 4.9V @ 1 kHz.
7: TSSOP devices are only specified at 25°C and +85°C.
8: For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency.
9: 4.5V - 5.5V is the supply voltage range for specified performance.