MCP3202 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Features Description • • • • • The MCP3202 is a successive approximation 12-bit analog-to-digital (A/D) converter with on-board sample and hold circuitry.
MCP3202 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD - VSS .........................................
MCP3202 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V, TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE. Parameter High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters: Clock Frequency Sym Min. Typ. Max. Units VOH VOL ILI ILO CIN, COUT 4.1 — -10 -10 — — — — — — — 0.
MCP3202 tCSH CS tSUCS tHI tLO CLK tSU DIN tHD MSB IN tEN DOUT FIGURE 1-1: DS21034F-page 4 tR tDO NULL BIT MSB OUT tF tDIS LSB Serial Timing. 1999-2011 Microchip Technology Inc.
MCP3202 Load Circuit for tDIS and tEN Load Circuit for tR, tF, tDO Test Point 1.
MCP3202 2.0 TYPICAL PERFORMANCE CHARACTERISTICS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 1.0 0.6 0.6 0.4 0.4 0.2 0.0 Negative INL -0.2 VDD = 2.7V fSAMPLE = 50 ksps 0.8 Positive INL INL (LSB) INL (LSB) 0.8 Positive INL 0.2 0.0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 Negative INL -1.0 -1.0 -50 -25 0 25 50 75 -50 100 -25 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-7: vs. Temperature.
MCP3202 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) DNL (LSB) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 0.2 0.0 -0.2 -0.4 VDD = 2.7V fSAMPLE = 50 ksps 0.2 0.0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 512 1024 1536 2048 2560 3072 3584 0 4096 512 1024 1536 Digital Code 0.8 0.6 0.6 Positive DNL DNL (LSB) DNL (LSB) 1.0 0.8 0.2 0.0 Negative DNL -0.4 0.0 25 50 75 Negative DNL -0.4 -0.8 -1.
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 2.0 1.8 VDD = 2.7V fSAMPLE = 50 ksps 0.6 0.4 Offset Error (LSB) Gain Error (LSB) 0.8 0.2 0.0 -0.2 -0.4 -0.6 VDD = 5V fSAMPLE = 100 -0.8 -1.0 -50 -25 0 25 50 75 VDD = 5V fSAMPLE = 100 ksps 1.6 1.4 1.2 1.0 0.8 VDD = 2.7V fSAMPLE = 50 ksps 0.6 0.4 0.2 0.0 -50 100 -25 0 Temperature (°C) FIGURE 2-19: FIGURE 2-22: Temperature. 75 100 Offset Error vs.
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 12.0 12.0 fSAMPLE = 50ksps 11.5 FSAMPLE = 100 ksps 11.0 ENOB (rms) ENOB (rms) VDD = 5V 11.5 11.0 fSAMPLE = 100 ksps 10.5 10.0 10.5 10.0 9.5 9.0 9.5 VDD = 2.7V 8.5 9.0 2.0 2.5 3.0 3.5 4.0 4.5 FSAMPLE = 50 ksps 8.0 5.0 1 10 VDD (V) FIGURE 2-25: (ENOB) vs. VDD. 100 Input Frequency (kHz) Effective Number of Bits FIGURE 2-28: Effective Number of Bits (ENOB) vs.
MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 500 at VDD = 2.5V, FCLK = 900 kHz 400 CS = VDD 70 350 60 300 50 IDDS (pA) IDD (µA) 80 All points at FCLK = 1.8 MHz except 450 250 200 40 30 150 20 100 10 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-31: 4.0 IDD vs. VDD. IDDS vs. VDD. FIGURE 2-34: 500 100.00 450 400 10.
MCP3202 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3.1. Additional descriptions of the device pins follows. TABLE 3-1: PIN FUNCTION TABLE MSOP, PDIP, SOIC, TSSOP Name 1 CS/SHDN 2 CH0 Channel 0 Analog Input 3 CH1 Channel 1 Analog Input 4 VSS Ground 5 DIN Serial Data In 6 DOUT Serial Data Out 7 CLK Serial Clock 8 VDD/VREF 3.1 Function Chip Select/Shutdown Input +2.7V to 5.
MCP3202 4.0 DEVICE OPERATION The MCP3202 A/D converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code.
MCP3202 VDD RSS Sampling Switch VT = 0.6V CHx CPIN 7 pF VA VT= 0.6V SS ILEAKAGE ±1 nA RS = 1 kW CSAMPLE = DAC capacitance = 20 pF VSS Legend VA RSS CHx CPIN VT ILEAKAGE SS RS CSAMPLE FIGURE 4-1: = = = = = = = = = signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance Analog Input Model. Clock Frequency (MHz) 2.0 1.8 VDD = 5V 1.6 1.4 1.2 1.
MCP3202 5.0 SERIAL COMMUNICATIONS 5.1 Overview Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit.
MCP3202 tCYC tCSH CS tSUCS Power Down HI-Z DOUT tSAMPLE MSBF SGL/ DIFF ODD/ SIGN DIN Start CLK Don’t Care Null B11 B10 B9 Bit B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 * HI-Z (MSB) tDATA ** tCONV * After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeros indefinitely.
MCP3202 6.0 APPLICATIONS INFORMATION 6.1 Using the MCP3202 with Microcontroller (MCU) SPI Ports Figure 6-1 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the ‘high’ state. With most microcontroller SPI ports, it is required to send groups of eight bits.
MCP3202 6.2 Maintaining Minimum Clock Speed When the MCP3202 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.
MCP3202 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead MSOP (3x3 mm) Example 3202CI 130256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (3.90 mm) Example 3202-B I/P 3 256 1130 Example 3202-BI SN 3 1130 NNN Legend: XX...
MCP3202 Package Marking Information (Continued) 8-Lead TSSOP (4.4 mm) Example 202C 1130 256 Legend: XX...X Y YY WW NNN e3 * Note: DS21034F-page 20 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
MCP3202 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1999-2011 Microchip Technology Inc.
MCP3202 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21034F-page 22 1999-2011 Microchip Technology Inc.
MCP3202 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1999-2011 Microchip Technology Inc.
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MCP3202 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1999-2011 Microchip Technology Inc.
MCP3202 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21034F-page 26 1999-2011 Microchip Technology Inc.
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MCP3202 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 1999-2011 Microchip Technology Inc.
MCP3202 APPENDIX A: REVISION HISTORY Revision F (November 2011) Updated Product Identification System Corrected MSOP package marking drawings. Updated Package Specification Drawings with new additions. Revision E (December 2008) Updates to packaging outline drawings. Revision D (December 2006) Updates to packaging outline drawings. Revision C (August 2001) Undocumented changes. Revision B (June 2000) Undocumented changes. Revision A (August 1999) Initial release of this document.
MCP3202 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP3202 NOTES: DS21034F-page 32 1999-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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