Datasheet
MCP3201
DS21290F-page 22 1998-2011 Microchip Technology Inc.
6.2 Maintaining Minimum Clock Speed
When the MCP3201 initiates the sample period, charge
is stored on the sample capacitor. When the sample
period is complete, the device converts one bit for each
clock that is received. It is important for the user to note
that a slow clock rate will allow charge to bleed off the
sample cap while the conversion is taking place. At
85°C (worst-case condition), the part will maintain
proper charge on the sample capacitor for at least
1.2 ms after the sample period has ended. This means
that the time between the end of the sample period and
the time that all 12 data bits have been clocked out
must not exceed 1.2 ms (effective clock frequency of
10 kHz). Failure to meet this criteria may induce
linearity errors into the conversion outside the rated
specifications. It should be noted that during the entire
conversion cycle, the A/D Converter does not require a
constant clock speed or duty cycle, as long as all timing
specifications are met.
6.3 Buffering/Filtering the Analog
Inputs
If the signal source for the A/D Converter is not a low-
impedance source, it will have to be buffered
or inaccurate conversion results may occur.
See Figure 4-2. It is also recommended that a filter be
used to eliminate any signals that may be aliased back
into the conversion results. This is illustrated in
Figure 6-3 where an op amp is used to drive the analog
input of the MCP3201 device. This amplifier provides a
low-impedance source for the converter input and a
low-pass filter, which eliminates unwanted high-
frequency noise.
Low-pass (anti-aliasing) filters can be designed using
Microchip’s interactive FilterLab
®
software. FilterLab
will calculate capacitor and resistor values, as well as
determine the number of poles that are required for the
application. For more information on filtering signals,
see application note AN699 “Anti-Aliasing Analog
Filters for Data Acquisition Systems.”
FIGURE 6-3: The MCP601 Operational
Amplifier is used to implement a 2nd order anti-
aliasing filter for the signal being converted by
the MCP3201 device.
MCP3201
V
DD
10 µF
IN-
IN+
-
+
V
IN
C
1
C
2
V
REF
4.096V
Reference
1µF
10 µF
0.1 µF
MCP601
R
1
R
2
R
3
R
4
MCP1541
C
L