Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsData collecting ICsData acquisition IC - AD converter (ADC) External SOT 23 5

 2003-2013 Microchip Technology Inc. DS21805B-page 1

MCP3021

Features

• 10-bit resolution

• ±1 LSB DNL, ±1 LSB INL max.

• 250 µA max conversion current

• 5 nA typical standby current, 1 µA max.

•I

C™ compatible serial interface

-100kHz I

C Standard mode

-400kHz I

C Fast mode

• Up to 8 devices on single 2-wire bus

• 22.3 ksps in I

C Fast mode

• Single-ended analog input channel

• On-chip sample and hold

• On-chip conversion clock

• Single supply specified operation: 2.7V to 5.5V

• Temperature range:

- Extended: -40°C to +125°C

•Small SOT-23 package

Applications

• Data Logging

• Multi-zone Monitoring

• Hand Held Portable Applications

• Battery Powered Test Equipment

• Remote or Isolated Data Acquisition

Package Type

Description

The Microchip Technology Inc. MCP3021 is a succes-

sive approximation A/D converter (ADC) with 10-bit

resolution. Available in the SOT-23 package, this

device provides one single-ended input with very low

power consumption. Based on an advanced CMOS

technology, the MCP3021 provides a low maximum

conversion current and standby current of 250 µA and

1 µA, respectively. Low current consumption, com-

bined with the small SOT-23 package, make this device

ideal for battery-powered and remote data acquisition

applications.

Communication to the MCP3021 is performed using a

2-wire I

C compatible interface. Standard (100 kHz)

and Fast (400 kHz) I

C modes are available with the

device. An on-chip conversion clock enables indepen-

dent timing for the I

C and conversion clocks. The

device is also addressable, allowing up to eight devices

on a single 2-wire bus.

The MCP3021 runs on a single supply voltage that

operates over a broad range of 2.7V to 5.5V. This

device also provides excellent linearity of ±1 LSB differ-

ential non-linearity (DNL) and ±1 LSB integral non-

linearity (INL), maximum.

Functional Block Diagram

5-Pin SOT-23A

SCL

AIN

MCP3021

SDA

Comparator

10-Bit SAR

DAC

AIN

SCL SDA

Clock

Control Logic

–

Sample

and

Hold

C™

Interface

Low Power 10-Bit A/D Converter With I

C™ Interface

Summary of content (26 pages)

PAGE 1
MCP3021 Low Power 10-Bit A/D Converter With I2C™ Interface Features Description • • • • • The Microchip Technology Inc. MCP3021 is a successive approximation A/D converter (ADC) with 10-bit resolution. Available in the SOT-23 package, this device provides one single-ended input with very low power consumption. Based on an advanced CMOS technology, the MCP3021 provides a low maximum conversion current and standby current of 250 µA and 1 µA, respectively.
PAGE 2
MCP3021 1.0 ELECTRICAL CHARACTERISTICS PIN FUNCTION TABLE Name Absolute Maximum Ratings † VDD...................................................................................7.0V Analog input pin w.r.t. VSS .......... ............. -0.6V to VDD +0.6V SDA and SCL pins w.r.t. VSS........... .........-0.6V to VDD +1.0V Storage temperature .....................................-65°C to +150°C Function VDD +2.7V to 5.
PAGE 3
MCP3021 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k TA = -40°C to +85°C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameters Input leakage current Output leakage current Sym Min Typ Max Units Conditions ILI -1 — +1 µA VIN = VSS to VDD ILO -1 — +1 µA VOUT = VSS to VDD CIN, COUT — — 10 pF TAMB = 25°C, f = 1 MHz; (Note 2) CB — — 400 pF SDA drive low, 0.
PAGE 4
MCP3021 TIMING SPECIFICATIONS Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TA = -40°C to +85°C.
PAGE 5
MCP3021 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
PAGE 6
MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.25 1 0.25 1 0.20 0.8 Positive INL 0.15 0.6 0.10 0.4 0.005 0.2 Positive INL 0.10 0.4 INL (LSB) INL (LSB) 0.20 0.8 0.15 0.6 0 -0.005 -0.2 -0.10 -0.4 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative INL -0.15 -0.6 -0.15 -0.6 -0.20 -0.8 -0.20 -0.8 -0.25 -1 Negative INL -0.
PAGE 7
MCP3021 0.5 0.5 0.4 0.4 0.3 0.3 0.2 0.2 DNL (LSB) DNL (LSB) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 0.1 0 -0.1 0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 -0.4 -0.4 -0.5 -0.5 0 256 512 768 1024 0 256 512 Digital Code FIGURE 2-13: DNL vs. Code (Representative Part). 1 0.25 0.20 0.8 0.20 0.8 0.15 0.6 0.15 0.6 0.005 0.2 0 -0.005 -0.2 -0.10 -0.4 Negative DNL -0.15 -0.
PAGE 8
MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 1.5 0.375 2 0.50 0.45 1.8 0.40 1.6 Offset Error (LSB) Gain Error (LSB) 0.2501 0.5 0.125 0 VDD = 2.7V -0.125 -0.5 -0.250 -1 VDD = 5V -0.375 -1.5 -50 -25 0.35 1.4 0.25 1 0.20 0.8 0.15 0.6 0.10 0.4 0.05 0.2 00 0 25 50 75 100 VDD = 5V 0.30 1.2 125 -50 VDD = 2.7V -25 0 Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature.
PAGE 9
MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 12 10 10 12 9.95 11.95 9.5 11.5 9.90 11.9 ENOB (rms) ENOB (rms) 9.85 11.85 9.80 11.8 9.75 11.75 9.70 11.7 VDD = 2.7V 9.0 11 8.5 10.5 9.65 11.65 9.60 11.6 9.55 11.55 8.0 10 7.7 9.5 9.50 11.5 2.5 7.0 9 3 3.5 4 4.5 5 5.5 1 10 VDD (V) FIGURE 2-25: Input Frequency (kHz) FIGURE 2-28: ENOB vs. VDD.
PAGE 10
MCP3021 200 100 180 90 160 80 140 70 120 100 IDDA (µA) IDD (µA) Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. VDD = 5V 80 60 50 VDD = 5V 40 30 60 VDD = 2.7V 20 40 VDD = 2.7V 20 10 0 0 0 100 200 300 0 400 100 200 2 FIGURE 2-31: Rate. 300 400 2 I C Clock Rate (kHz) I C Clock Rate (kHz) IDD (Conversion) vs. Clock FIGURE 2-34: Rate. IDDA (Active Bus) vs.
PAGE 11
MCP3021 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25°C. 2.1 Test Circuit 1000 100 VDD = 5V IDDS (nA) 10 1 0.1 10 µF 0.1 µF 0.01 2 k 0.001 AIN 0.0001 -50 -25 0 25 50 75 100 125 Temperature (°C) FIGURE 2-37: Temperature. VIN VDD 2 k SDA MCP3021 VSS SCL IDDS (Standby) vs. VCM = 2.5V 2 Analog Input Leakage (nA) 1.8 1.6 FIGURE 2-39: Typical Test Configuration. 1.4 1.2 1 0.
PAGE 12
MCP3021 3.0 PIN FUNCTIONS TABLE 3-1: PIN FUNCTION TABLE Name 3.1 Function VDD +2.7V to 5.5V Power Supply VSS Ground AIN Analog Input SDA Serial Data In/Out SCL Serial Clock In VDD and VSS The VDD pin, with respect to VSS, provides power to the device, as well as a voltage reference for the conversion process. Refer to Section 6.4, “Device Power and Layout Considerations”, for tips on power and grounding. 3.
PAGE 13
MCP3021 4.0 DEVICE OPERATION 4.2 The conversion time is the time required to obtain the digital result once the analog input is disconnected from the holding capacitor. With the MCP3021, the specified conversion time is typically 8.96 µs. This time is dependent on the internal oscillator and independent of SCL. The MCP3021 employs a classic SAR architecture. This architecture uses an internal sample and hold capacitor to store the analog input while the conversion is taking place.
PAGE 14
MCP3021 4.5 Differential Non-Linearity (DNL) In the ideal ADC transfer function, each code has a uniform width. That is, the difference in analog input voltage is constant from one code transition point to the next. DNL specifies the deviation of any code in the transfer function from an ideal code width of 1 LSB. The DNL is determined by subtracting the locations of successive code transition points after compensating for any gain and offset errors.
PAGE 15
MCP3021 5.0 SERIAL COMMUNICATIONS 5.1 I2C Bus Characteristics The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (refer to Figure 5-1). 5.1.
PAGE 16
MCP3021 Device Addressing 5.3 The address byte is the first byte received following the START condition from the master device. The first part of the control byte consists of a 4-bit device code, which is set to 1001 for the MCP3021. The device code is followed by three address bits: A2, A1 and A0. The default address bits are 101 (contact the Microchip factory for additional address bit options).
PAGE 17
MCP3021 The input signal will initially be sampled with the first falling edge of the clock following the transmission of a logic-high R/W bit. Additionally, with the rising edge of the SCL, the ADC will transmit an acknowledge bit (ACK = 0). The master must release the data bus during this clock pulse to allow the MCP3021 to pull the line low (refer to Figure 5-3). For consecutive samples, sampling begins on the last bit of the lower data byte. Refer to Figure 5-6 for timing diagram. 5.3.
PAGE 18
MCP3021 6.0 APPLICATIONS INFORMATION 6.1 Driving the Analog Input The MCP3021 has a single-ended analog input (AIN). For proper conversion results, the voltage at the AIN pin must be kept between VSS and VDD. If the converter has no offset error, gain error, INL or DNL errors and the voltage level of AIN is equal to or less than VSS + 1/2 LSB, the resultant code will be 000h. Additionally, if the voltage at AIN is equal to or greater than VDD - 1.5 LSB, the output code will be 1FFh.
PAGE 19
MCP3021 6.3 Device Polling In some instances, it may be necessary to test for MCP3021 presence on the I2C bus without performing a conversion, described in Figure 6-4. Here we are setting the R/W bit in the address byte to a zero. The MCP3021 will then acknowledge by pulling SDA low during the ACK clock and then release the bus back to the I2C master. A stop or repeated start bit can then be issued from the master and I2C communication can continue.
PAGE 20
MCP3021 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 5-Pin SOT-23A (EIAJ SC-74) Device 3 2 1  4 Part Number 5 Address Option SOT-23 MCP3021A0T-E/OT 000 GP MCP3021A1T-E/OT 001 GS MCP3021A2T-E/OT 010 GK MCP3021A3T-E/OT 011 GL MCP3021A4T-E/OT 100 GM MCP3021A5T-E/OT 101 GJ * MCP3021A6T-E/OT 110 GQ MCP3021A7T-E/OT 111 GR * Default option. Contact Microchip Factory for other address options. Legend: XX...
PAGE 21
MCP3021 5-Lead Plastic Small Outline Transistor (OT) (SOT23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PAGE 22
MCP3021 8.0 REVISION HISTORY Revision B (January 2013) Added a note to each package outline drawing. DS21805B-page 22  2003-2013 Microchip Technology Inc.
PAGE 23
MCP3021 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
PAGE 24
MCP3021 NOTES: DS21805B-page 24  2003-2013 Microchip Technology Inc.
PAGE 25
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 26
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