Datasheet

 2000-2011 Microchip Technology Inc. DS21294E-page 13
MCP3002
4.0 DEVICE OPERATION
The MCP3002 A/D converter employs a conventional
SAR architecture. With this architecture, a sample is
acquired on an internal sample/hold capacitor for
1.5 clock cycles starting on the second rising edge of
the serial clock after the start bit has been received.
Following this sample time, the input switch of the con-
verter opens and the device uses the collected charge
on the internal sample and hold capacitor to produce a
serial 10-bit digital output code.
Conversion rates of 200 ksps are possible on the
MCP3002. See Section 6.2 “Maintaining Minimum
Clock Speed” for information on minimum clock rates.
Communication with the device is done using a 3-wire
SPI-compatible interface.
4.1 Analog Inputs
The MCP3002 device offers the choice of using the ana-
log input channels configured as two single-ended
inputs that are referenced to V
SS
or a single pseudo-
differential input. The configuration setup is done as part
of the serial command before each conversion begins.
When used in the pseudo-differential mode, CH0 and
CH1 are programmed as the IN+ and IN- inputs as part
of the command string transmitted to the device. The
IN+ input can range from IN- to the reference voltage,
V
DD
. The IN- input is limited to ±100 mV from the V
SS
rail. The IN- input can be used to cancel small signal
common-mode noise which is present on both the IN+
and IN- inputs.
For the A/D converter to meet specification, the charge
holding capacitor (C
SAMPLE
) must be given enough
time to acquire a 10-bit accurate voltage level during
the 1.5 clock cycle sampling period. The analog input
model is shown in Figure 4-1.
In this diagram, it is shown that the source impedance
(R
S
) adds to the internal sampling switch (R
SS
) imped-
ance, directly affecting the time that is required to
charge the capacitor, C
SAMPLE
. Consequently, larger
source impedances increase the offset, gain, and
integral linearity errors of the conversion.
Ideally, the impedance of the signal source should be
near zero. This is achievable with an operational amp
lifer such as the MCP601 which has a closed loop out-
put impedance of tens of ohms. The adverse affects of
higher source impedances are shown in Figure 4-2.
When operating in the pseudo-differential mode, if the
voltage level of IN+ is equal to or less than IN-, the
resultant code will be 000h. If the voltage at IN+ is equal
to or greater than {[V
DD
+ (IN-)] - 1 LSB}, then the out-
put code will be 3FFh. If the voltage level at IN- is more
than 1 LSB below V
SS
, then the voltage level at the IN+
input will have to go below V
SS
to see the 000h output
code. Conversely, if IN- is more than 1 LSB above
V
SS
, then the 3FFh code will not be seen unless the
IN+ input level goes above V
DD
level. If the voltage at
IN+ is equal to or greater than {[V
DD
+ (IN-)] - 1 LSB},
then the output code will be 3FFh.
4.2 Digital Output Code
The digital output code produced by an A/D Converter
is a function of the input signal and the reference
voltage. For the MCP3002, V
DD
is used as the
reference voltage.
As the V
DD
level is reduced, the LSB size is reduced
accordingly. The theoretical digital output code
produced by the A/D Converter is shown below.
LSB Size
V
REF
1024
--------------=
Digital Output Code
1024*V
IN
V
DD
-------------------------=
Where:
V
IN
= analog input voltage
V
DD
= supply voltage