Datasheet
Table Of Contents
- Features
- Applications
- Description
- Package Types
- Functional Block Diagram
- 1.0 Electrical Characteristics
- PIN FUNCTION TABLE
- electrical characteristics
- 2.0 Typical Performance Characteristics
- FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate.
- FIGURE 2-2: Integral Nonlinearity (INL) vs. Vref.
- FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
- FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (Vdd = 2.7V).
- FIGURE 2-5: Integral Nonlinearity (INL) vs. Vref (Vdd = 2.7V).
- FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, Vdd = 2.7V).
- FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature.
- FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
- FIGURE 2-9: Differential Nonlinearity (DNL) vs. Vref.
- FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (Vdd = 2.7V).
- FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (Vdd = 2.7V).
- FIGURE 2-12: Differential Nonlinearity (DNL) vs. Vref (Vdd = 2.7V).
- FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
- FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.
- FIGURE 2-15: Gain Error vs. Vref.
- FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, Vdd = 2.7V).
- FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (Vdd = 2.7V).
- FIGURE 2-18: Offset Error vs. Vref.
- FIGURE 2-19: Gain Error vs. Temperature.
- FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency.
- FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
- FIGURE 2-22: Offset Error vs. Temperature.
- FIGURE 2-23: Signal to Noise Ratio and Distortion (SINAD) vs. Input Frequency.
- FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level.
- FIGURE 2-25: Effective Number of Bits (ENOB) vs. Vref.
- FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.
- FIGURE 2-27: Frequency Spectrum of 10kHz Input (Representative Part).
- FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
- FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
- FIGURE 2-30: Frequency Spectrum of 1kHz Input (Representative Part, Vdd = 2.7V).
- FIGURE 2-31: Idd vs. Vdd.
- FIGURE 2-32: Idd vs. Clock Frequency.
- FIGURE 2-33: Idd vs. Temperature.
- FIGURE 2-34: Iref vs. Vdd.
- FIGURE 2-35: Iref vs. Clock Frequency.
- FIGURE 2-36: Iref vs. Temperature.
- FIGURE 2-37: Idds vs. Vdd.
- FIGURE 2-38: Idds vs. Temperature.
- FIGURE 2-39: Analog Input Leakage Current vs. Temperature.
- 3.0 Pin Descriptions
- 4.0 Device Operation
- 5.0 Serial Communications
- 6.0 Applications Information
- 7.0 Packaging Information
- Appendix A: Revision History
- Product Identification System
- Worldwide Sales and Service
MCP3001
DS21293C-page 16 © 2007 Microchip Technology Inc.
6.0 APPLICATIONS INFORMATION
6.1 Using the MCP3001 with
Microcontroller SPI Ports
With most microcontroller SPI ports, it is required to
clock out eight bits at a time. If this is the case, it will be
necessary to provide more clocks than are required for
the MCP3001. As an example, Figure 6-1 and
Figure 6-2 show how the MCP3001 can be interfaced
to a microcontroller with a standard SPI port. Since the
MCP3001 always clocks data out on the falling edge of
clock, the MCU SPI port must be configured to match
this operation. SPI Mode 0,0 (clock idles low) and SPI
Mode 1,1 (clock idles high) are both compatible with
the MCP3001. Figure 6-1 depicts the operation shown
in SPI Mode 0,0, which requires that the CLK from the
microcontroller idles in the ‘low’ state. As shown in the
diagram, the MSB is clocked out of the ADC on the fall-
ing edge of the third clock pulse. After the first eight
clocks have been sent to the device, the microcontrol-
ler’s receive buffer will contain two unknown bits (the
output is at high impedance for the first two clocks), the
null bit and the highest order five bits of the conversion.
After the second eight clocks have been sent to the
device, the MCU receive register will contain the lowest
order five bits and the B1-B4 bits repeated as the ADC
has begun to shift out LSB first data with the extra
clocks. Typical procedure would then call for the lower
order byte of data to be shifted right by three bits to
remove the extra B1-B4 bits. The B9-B5 bits are then
rotated 3 bits to the right with B7-B5 rotating from the
high order byte to the lower order byte. Easier manipu-
lation of the converted data can be obtained by using
this method.
Figure 6-2 shows SPI Mode 1,1 communication which
requires that the clock idles in the high state. As with
mode 0,0, the ADC outputs data on the falling edge of
the clock and the MCU latches data from the ADC in on
the rising edge of the clock.
FIGURE 6-1: SPI Communication with the MCP3001 using 8-bit segments (Mode 0,0: SCLK idles low).
FIGURE 6-2: SPI Communication with the MCP3001 using 8-bit segments (Mode 1,1: SCLK idles high).
CS
CLK 910111213141516
D
OUT
NULL
BIT
B9 B8 B7 B6
B5
B4 B3 B2 B1 B0 B1 B2
HI-Z
B5 B4 B3 B2 B1 B0 B1 B2B9 B8 B7 B6??0
MCU latches data from ADC
Data is clocked out of
ADC on falling edges
on rising edges of SCLK
12345678
HI-Z
B3
B3
LSB first data begins
to come out
B4
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits
CS
CLK
910111213141516
D
OUT
NULL
BIT
B9 B8 B7 B6
B5
B4 B3 B2 B1 B0 B1 B2
HI-Z
B5
B4 B3 B2 B1 B0 B1 B2
B9 B8 B7 B6??0
MCU latches data from ADC
Data is clocked out of
ADC on falling edges
on rising edges of SCLK
1234567
8
B3
B3
LSB first data begins
to come out
HI-Z
Data stored into MCU receive register
after transmission of first 8 bits
Data stored into MCU receive register
after transmission of second 8 bits