Datasheet
Table Of Contents
- Features
- Applications
- Description
- Package Types
- Functional Block Diagram
- 1.0 Electrical Characteristics
- PIN FUNCTION TABLE
- electrical characteristics
- 2.0 Typical Performance Characteristics
- FIGURE 2-1: Integral Nonlinearity (INL) vs. Sample Rate.
- FIGURE 2-2: Integral Nonlinearity (INL) vs. Vref.
- FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part).
- FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (Vdd = 2.7V).
- FIGURE 2-5: Integral Nonlinearity (INL) vs. Vref (Vdd = 2.7V).
- FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, Vdd = 2.7V).
- FIGURE 2-7: Integral Nonlinearity (INL) vs. Temperature.
- FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate.
- FIGURE 2-9: Differential Nonlinearity (DNL) vs. Vref.
- FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (Vdd = 2.7V).
- FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (Vdd = 2.7V).
- FIGURE 2-12: Differential Nonlinearity (DNL) vs. Vref (Vdd = 2.7V).
- FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part).
- FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature.
- FIGURE 2-15: Gain Error vs. Vref.
- FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, Vdd = 2.7V).
- FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (Vdd = 2.7V).
- FIGURE 2-18: Offset Error vs. Vref.
- FIGURE 2-19: Gain Error vs. Temperature.
- FIGURE 2-20: Signal to Noise Ratio (SNR) vs. Input Frequency.
- FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency.
- FIGURE 2-22: Offset Error vs. Temperature.
- FIGURE 2-23: Signal to Noise Ratio and Distortion (SINAD) vs. Input Frequency.
- FIGURE 2-24: Signal to Noise and Distortion (SINAD) vs. Input Signal Level.
- FIGURE 2-25: Effective Number of Bits (ENOB) vs. Vref.
- FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.
- FIGURE 2-27: Frequency Spectrum of 10kHz Input (Representative Part).
- FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency.
- FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency.
- FIGURE 2-30: Frequency Spectrum of 1kHz Input (Representative Part, Vdd = 2.7V).
- FIGURE 2-31: Idd vs. Vdd.
- FIGURE 2-32: Idd vs. Clock Frequency.
- FIGURE 2-33: Idd vs. Temperature.
- FIGURE 2-34: Iref vs. Vdd.
- FIGURE 2-35: Iref vs. Clock Frequency.
- FIGURE 2-36: Iref vs. Temperature.
- FIGURE 2-37: Idds vs. Vdd.
- FIGURE 2-38: Idds vs. Temperature.
- FIGURE 2-39: Analog Input Leakage Current vs. Temperature.
- 3.0 Pin Descriptions
- 4.0 Device Operation
- 5.0 Serial Communications
- 6.0 Applications Information
- 7.0 Packaging Information
- Appendix A: Revision History
- Product Identification System
- Worldwide Sales and Service
© 2007 Microchip Technology Inc. DS21293C-page 15
MCP3001
5.0 SERIAL COMMUNICATIONS
Communication with the device is done using a stan-
dard SPI compatible serial interface. Initiating commu-
nication with the MCP3001 begins with the CS going
low. If the device was powered up with the CS
pin low,
it must be brought high and back low to initiate commu-
nication. The device will begin to sample the analog
input on the first rising edge after CS
goes low. The
sample period will end in the falling edge of the second
clock, at which time the device will output a low null bit.
The next 10 clocks will output the result of the conver-
sion with MSB first, as shown in Figure 5-1. Data is
always output from the device on the falling edge of the
clock. If all 10 data bits have been transmitted and the
device continues to receive clocks while the CS
is held
low, the device will output the conversion result LSB
first, as shown in Figure 5-2. If more clocks are pro-
vided to the device while CS
is still low (after the LSB
first data has been transmitted), the device will clock
out zeros indefinitely.
If it is desired, the CS
can be raised to end the conver-
sion period at any time during the transmission. Faster
conversion rates can be obtained by using this tech-
nique if not all the bits are captured before starting a
new cycle. Some system designers use this method by
capturing only the highest order 8 bits and ‘throwing
away’ the lower 2 bits.
FIGURE 5-1: Communication with MCP3001 (MSB first Format).
FIGURE 5-2: Communication with MCP3001 (LSB first Format).
CS
CLK
D
OUT
t
CYC
Power
Down
t
SUCS
t
SAMPLE
t
CONV
t
DATA
**
* After completing the data transfer, if further clocks are applied with CS
low, the ADC will output LSB first data,
followed by zeros indefinitely. See Figure below.
** t
DATA
: during this time, the bias current and the comparator powers down and the reference input becomes a
high impedance node.
t
CSH
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*
HI-Z
HI-Z
NULL
BIT
B9 B8 B7 B6
NULL
BIT
CS
CLK
D
OUT
t
CYC
Power Down
t
SUCS
t
SAMPLE
t
CONV
t
DATA
**
* After completing the data transfer, if further clocks are applied with CS
low, the ADC will output zeros indefi-
nitely.
** t
DATA
: during this time, the bias current and the comparator powers down and the reference input becomes a
high impedance node leaving the CLK running to clock out the LSB-first data or zeros.
t
CSH
NULL
BIT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
HI-Z
B1 B2 B3
B4
B5 B6 B7 B8 B9
HI-Z