Datasheet

© 2007 Microchip Technology Inc. DS21664D-page 7
MCP2502X/5X
REGISTER 2-1: TEC - TRANSMITTER ERROR COUNTER
REGISTER 2-2: REC - RECEIVER ERROR COUNTER
FIGURE 2-3: BIT TIME PARTITIONING
2.4 Bit Timing Logic
The Bit Timing Logic (BTL) monitors the bus line input
and handles the bus-related bit timing based on the
CAN protocol. The BTL synchronizes on a recessive-
to-dominant bus transition at Start-of-Frame (hard
synchronization) and on any further recessive-to-
dominant bus line transition if the CAN controller itself
does not transmit a dominant bit (resynchronization).
The BTL also provides programmable time segments
to compensate for the propagation delay time, phase
shifts and to define the position of the sample point
within the bit time. These programmable segments are
made up of integer units called Time Quanta (T
Q). The
nominal bit time is calculated by programming the T
Q
length and the number of TQ in each time segment, as
discussed below.
2.4.1 TIME QUANTUM (TQ)
Time Quantum is a fixed unit of time derived from the
oscillator period. There is a programmable baud rate
prescaler (BRP) (with integral values ranging from 1 to
64) as well as a fixed division by two for clock
generation.
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0
bit 7 bit 0
bit 7-0 TEC7:TEC0: Transmit Error Counter bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0
bit 7 bit 0
bit 7-0 REC7:REC0: Receive Error Counter bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Input Signal
Sync
Prop
Segment
Phase
Segment 1
Phase
Segment 2
Sample Point
TQ