Datasheet

MCP2502X/5X
DS21664D-page 28 © 2007 Microchip Technology Inc.
If the Error Condition message is enabled
(OPTREG2.TXONE = 1) and one of the above
conditions occur, the MCP2502X/5X sends TXID1
identifier with output message Read CAN Error States
data field (three data bytes).
4.5.4 SCHEDULED TRANSMISSIONS
The MCP2502X/5X has the capability of sending
scheduled transmissions (On Bus message), if
enabled.
The scheduled transmission control register (STCON)
enables and configures the occurrence of the
scheduled message. Setting the STEN bit in the
STCON register enables the scheduled message. The
STBF1:STBF0 and STM3:STM0 bits allow a scheduled
transmission to be initiated from a minimum of 256 µs
to a maximum of 16.8 seconds (using a 16 MHz
FOSC)
and the following equation:
Message Type - The message sent for scheduled
transmissions consists of either TXID0 with zero data
bytes or TXID0 with eight data bytes containing the
Read A/D Regs message, depending on STMS bit in
the STCON register.
REGISTER 4-1: STCON - SCHEDULED TRANSMISSION CONTROL REGISTER
Note: The actual scheduled transmission
intervals may vary slightly due to the
internal event que of the control module.
Scheduled Transmission
= STBF1:STBF0(STM3:STM0)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
STEN STMS STBF1 STBF0 STM3 STM2 STM1 STM0
bit 7 bit 0
bit 7 STEN: Scheduled Transmission Enable bits
1 = Enabled
0 =Disabled
bit 6 STMS: Scheduled Transmission Message Select
1 = Sends Transmit ID 0 (TXID0) with the “Read A/D Regs” data (DLC = 8)
0 = Sends Transmit ID 0 (TXID0) with no data (DLC = 0)
bit 5-4 STBF1:STBF0: Base Transmission Frequency bits
00 = 4096T
OSC
01 = 16•(4096TOSC)
10 = 256
•(4096TOSC)
10 = 4096
•(4096TOSC)
(e.g., STBF1:STBF0 => 00 => 256 µs for a 16 MHz F
OSC)
bit 3-0 STM3:STM0: Scheduled Transmission Multiplier bits
0000 = 1
0001 = 2
-
-
1110 = 15
1111 = 16
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown