MCP2502X/5X CAN I/O Expander Family Features Description • Implements CAN V2.
MCP2502X/5X Package Types Threshold Detection - refers to the MCP2502X/5X’s ability to automatically transmit a message when a predefined analog threshold is reached. PDIP/SOIC GP0/AN0 1 14 VDD GP1/AN1 2 13 TXCAN/TXRXCAN* GP2/AN2/PWM1 3 12 RXCAN/NC* GP3/AN3/PWM2 4 11 GP7/RST/VPP GP4/VREF- 5 10 GP6/CLKOUT GP5/VREF+ 6 9 OSC2 7 8 OSC1/CLKIN VSS * One-wire option available on MCP250X5 devices.
MCP2502X/5X 1.0 DEVICE OVERVIEW Figure 1-1 is the block diagram of the MCP2502X/5X and Table 1-1 is the pinout description. This document contains device-specific information on the MCP2502X/5X family of CAN I/O expanders. The CAN protocol is not discussed in depth in this document. Additional information on the CAN protocol can be found in the CAN specification, as defined by Robert Bosch GmbH. FIGURE 1-1: The following sections detail the modules as listed in Figure 1-1.
MCP2502X/5X NOTES: DS21664D-page 4 © 2007 Microchip Technology Inc.
MCP2502X/5X 2.0 CAN MODULE • One full-acceptance mask (standard and extended) • Two full-acceptance filters (standard and extended) • One filter for each receive buffer • Three prioritized transmit buffers for transmitting predefined message types • Automatic wake-up on bus traffic function • Error management logic for transmit and receive error states • Low-power SLEEP mode The CAN module is a protocol controller that converts between raw digital data and CAN message packets.
MCP2502X/5X 2.1 CAN Protocol Finite State Machine 2.3 The heart of the engine is the Finite State Machine (FSM). This state machine sequences through messages on a bit-by-bit basis, changing states as the fields of the various frame types are transmitted or received. The FSM is a sequencer controlling the sequential data stream between the TX/RX Shift register, the CRC register and the bus line.
MCP2502X/5X REGISTER 2-1: TEC - TRANSMITTER ERROR COUNTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 bit 7 bit 7-0 bit 0 TEC7:TEC0: Transmit Error Counter bits Legend: REGISTER 2-2: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown REC - RECEIVER ERROR COUNTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 bit 7 bit 7
MCP2502X/5X The base TQ is defined as twice the oscillator period. Adding the BRP into the equation yields: T Q = 2*T OSC * ( BRP + 1 ) where BRP = binary value represented by CNF1.BRP<5:0> By definition, the nominal bit time is programmable from a minimum of 8 TQ to 25 TQ. Also, the minimum nominal bit time is 1 µs, which corresponds to 1 Mb/s. 2.4.2 TIME SEGMENTS Time segments make up the nominal bit time.
MCP2502X/5X 2.4.6.2 As a result of resynchronization, PS1 may be lengthened or PS2 may be shortened. The amount of lengthening or shortening of the phase buffer segments has an upper-bound given by the SJW. The SJW is programmable between 1 TQ and 4 TQ. The value of the SJW will be added to PS1 (or subtracted from PS2) depending on the phase error (e) of the edge in relation to the receiver’s SyncSeg.
MCP2502X/5X REGISTER 2-4: CNF2 - CAN CONFIGURATION REGISTER 2 R/W-0 R/W-0 BTLMODE SAM R/W-0 R/W-0 PHSEG12 PHSEG11 R/W-0 R/W-0 R/W-0 R/W-0 PHSEG10 PRSEG2 PRSEG1 PRSEG0 bit 7 bit 0 bit 7 BTL MODE: Length determination of PHSEG2 bit 1 = Length of Phase_Seg2 determined by bits 2:0 of CNF3 0 = Length of Phase_Seg2 is the greater of Phase_Seg1 or IPT(2Tq) bit 6 SAM: Sample of the CAN bus line bit 1 = Bus line is sampled three times at the sample point 0 = Bus line is sampled once at the sampl
MCP2502X/5X 2.5 Buffers, Masks, and Filters This part of the CAN module supports the transmitting, receiving and acceptance of CAN messages. Three transmit buffers are used for the three transmit message IDs, as discussed later in this section. Two receive buffers store the CAN message’s arbitration field, control field and the data field. One mask defines which bits are to be applied to either filter. The mask can be regarded as defining “don’t care” bits for the filter.
MCP2502X/5X 2.7 Acceptance Mask The acceptance mask is used to define which bits in the CAN ID are to be compared against the programmable filters. Individual bits within the mask correspond to bits in the CAN ID that, in turn, correspond to bits in the acceptance filters. Any bit in the mask that is set to a ‘1’ will cause the corresponding CAN ID bit to be compared against the associated filter bit.
MCP2502X/5X REGISTER 2-7: TXIDNSIDL - TRANSMIT IDENTIFIER N STANDARD IDENTIFIER LOW R/W-x R/W-x R/W-x U-0 R/W-x U-0 R/W-x R/W-x SID2 SID1 SID0 — EXIDE — EID17 EID16 bit 7 bit 0 bit 7-5 SID2:SID0: Standard Identifier bits bit 4 Unimplemented: Read as '0’ bit 3 EXIDE: Extended Identifier Enable bit 1 = Message will transmit extended identifier 0 = Message will transmit standard identifier bit 2 Unimplemented: Read as '0’ bit 1-0 EID17:EID16: Extended Identifier bits Legend: REGIST
MCP2502X/5X REGISTER 2-10: RXMSIDH - ACCEPTANCE FILTER MASK STANDARD IDENTIFIER HIGH R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3* bit 7 bit 7-0 bit 0 SID10:SID3: Standard Identifier bits * If OPTREG2.MTYPE = 1, then SID3 is forced to zero.
MCP2502X/5X REGISTER 2-13: RXMEID0 - ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER LOW R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 bit 7 bit 0 bit 7-3 EID7:EID3: Extended Identifier bits bit 2-0 EID2:EID0: Extended Identifier bits (always reads as ‘0’) Legend: REGISTER 2-14: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RXFNSIDH - ACCEPTAN
MCP2502X/5X REGISTER 2-16: RXFNEID8 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER MID R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 7-0 bit 0 EID15:EID8: Extended Identifier Bit Legend: REGISTER 2-17: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown RXFNEID0 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER LOW R/W-x R/W-x R/W-x R/W-x R
MCP2502X/5X REGISTER 2-18: EFLG - ERROR FLAG REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ESCF RBO TXBO TXEP RXEP TXWAR RXWAR EWARN bit 7 bit 0 bit 7 ESCF: Error State Change (for sending Error state message) 1 = An error state change occurred 0 = No error state change bit 6 RBO: Receive Buffer Overflow 1 = Overflow occurred 0 = No overflow occurred bit 5 TXBO: Transmitter in Bus Off Error State bit 1 = TEC reaches 256 0 = Indicates a successful bus recovery sequence bit 4 TXEP: Transm
MCP2502X/5X NOTES: DS21664D-page 18 © 2007 Microchip Technology Inc.
MCP2502X/5X 3.0 USER REGISTERS 3.1 Description The MCP2502X/5X allows the user to pre-program registers pertaining to CAN module and device configuration into non-volatile EPROM memory. In this way, the device is initialized to a default state after power-up. The user registers are transferred to SRAM during the power-up sequence and many of the registers are able to be accessed via the CAN bus once the device establishes a connection with the bus.
MCP2502X/5X TABLE 3-1: Address USER MEMORY MAP (CONTINUED) Name Description 0Eh ADCON0 4 0Fh ADCON14 10h STCON Address Name Description A/D Control Register; contains enable, conversion rate, channel select bits 29h TXID2SIDL Transmit Buffer 2, Standard ID LSB, Extended ID USB, and Extended ID enable A/D Control Register; contains voltage reference source, conversion rate and A/D input enable bits 2Ah TXID2EID8 Transmit Buffer 2, Extended ID MSB Scheduled Transmission Control Register
MCP2502X/5X 4.0 DEVICE OPERATION 4.1 Power-Up Sequence The following sections describe the events/actions of the MCP2502X/5X during normal power-up and operation. 4.1.1 POWER-ON RESET The MCP2502X/5X goes through a sequence of events at power-on reset (POR) in order to load the programmed configuration and insure that errors are not introduced on the bus. During this time, the device is prevented from generating a low condition on the TXCAN pin.
MCP2502X/5X 4.3.1 INFORMATION REQUEST MESSAGES Information Request Messages (IRM) are messages that the MCP2502X/5X receives into Receive Buffer 0 (matches Filter 0) and then responds to by transmitting a message (output message) containing the requested data. IRMs can be implemented as either a Remote Transfer Request (RTR) or a Data Frame message by configuring the MTYPE bit in the OPTREG2 register.
MCP2502X/5X 4.3.2 OUTPUT MESSAGES The data frame sent in response to the information request message is defined as an output message. If the data fame is in response to a remote frame, it will have the same identifier (standard or extended) and contain the same number of data bytes specified by the DLC of the remote frame (per the CAN 2.0B specification).
MCP2502X/5X 4.4.3 TRANSMIT MESSAGE PRIORITY There is a priority for all transmit messages, including TXIDn and all “Output” messages. The transmit message priority is as follows: 1. 2. 3. 4. Output messages have the highest priority. Prioritization of the individual output message types is determined by the three bits that determine message type, with the lowest value having the highest priority (e.g., Read A/D Regs is a higher priority than Read Control Regs).
© 2007 Microchip Technology Inc.
COMMAND MESSAGES (EXTENDED IDENTIFIER) Information Request Messages (to MCP2502X/5X) Standard ID Extended ID 1987654321 0RI 0 T D RE Read A/D Regs Read Control Regs Read Config Regs Read CAN Error Read PWM Config Read User Mem Read User Mem Read Register x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DLC 1 0 0 0 0 1 1 0 0 1 1 0 1 0
MCP2502X/5X 4.5 Automatic Transmission The MCP2502X/5X can automatically initiate four different message types to indicate the following situations: • • • • Edge detected on a digital input (TXID2). Threshold exceeded on an analog input (TXID2). Error condition (Read Error output message). Scheduled transmissions (TXID0). The buffers have an implied transmit priority, where buffer 2 is the highest and buffer 0 is the lowest.
MCP2502X/5X If the Error Condition message is enabled (OPTREG2.TXONE = 1) and one of the above conditions occur, the MCP2502X/5X sends TXID1 identifier with output message Read CAN Error States data field (three data bytes). 4.5.4 SCHEDULED TRANSMISSIONS The MCP2502X/5X has the capability of sending scheduled transmissions (On Bus message), if enabled.
MCP2502X/5X TABLE 4-4: Addr Name 0Bh 0Ch REGISTERS ASSOCIATED WITH THE CAN MODULE bit7 bit6 bit5 bit4 bit3 bit2 CNF1 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 CNF2 BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 bit0 Value on POR Value on RST BRP1 BRP0 xxxx xxxx uuuu uuuu PRSEG1 PRSEG0 xxxx xxxx uuuu uuuu bit1 0Dh CNF3 — WAKF — — — PHSEG22 PHSEG21 PHSEG20 -x-- xxxx -u-- uuuu 10h STCON STEM STMS STBF1 STBF0 STM3 STM2 STM1 STM0 0xxx xxxx 0uuu uuuu 11h OPTREG2 CAEN
MCP2502X/5X NOTES: DS21664D-page 30 © 2007 Microchip Technology Inc.
MCP2502X/5X 5.0 GPIO MODULE 5.1 Description 5.2 The MCP2502X/5X has eight general-purpose input/ output pins (GP0 to GP7), collectively labeled GPIO. All GPIO port pins have TTL input levels and full CMOS output drivers, with the exception of GP7, which is input only. Pins GP6:GP0 can be individually configured as input or output via the GPDDR register. Note: The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs.
MCP2502X/5X REGISTER 5-1: GPDDR - DATA DIRECTION REGISTER U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-0 DDR6:DDR0: Data Direction Register* bits 1 = corresponding GPIO pin is configured as an input 0 = corresponding GPIO pin is configured as an output * must bet set if corresponding analog channel is enabled (see ADCON1) Legend: REGISTER 5-2: R = Readable bit W = Writable bit U = Unimplemented
MCP2502X/5X REGISTER 5-4: IOINTPO REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL bit 7 bit 7-0 bit 0 GP7POL:GP0POL: Transmit-on-change Polarity bits 1 = Digital Inputs: Low-to-High Transition On Corresponding GPIO Input Pin Generates a transmit message Analog Inputs: A/D result above compare value generates a transmit message 0 = Digital Inputs: High-to-Low Transition On Corresponding GPIO Input Generates transmit message A
MCP2502X/5X REGISTER 5-6: OPTREG1 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-0 R/W-0 R/W-0 GPPU CLKEN CLKPS1 CLKPS0 — CMREQ AQT1 AQT0 bit 7 bit 0 bit 7 GPPU: Weak pull-up enabled 1 = Weak pull-ups disabled 0 = Weak pull-ups enabled (GP7:GP0) bit 6 CLKEN: 1 = Clock Out Function disabled 0 = Clock Out Function enabled bit 5-4 CLKPS1:CLKPS0: CLKOUT Prescaler bits 00 = FOSC/1 01 = FOSC/2 10 = FOSC/4 11 = FOSC/8 bit 3 Reserved: bit 2 CMREQ: Requests mode of operation (allows mode change
MCP2502X/5X REGISTER 5-7: OPTREG2 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAEN ERREN TXONEN SLPEN MTYPE PDEFEN PUSLP PUNRM bit 7 bit 0 bit 7 CAEN: Command Acknowledge Enable bit 1 = Enables the command acknowledge message (TXID1) 0 = Enables the receive overflow message (TXID1) bit 6 ERREN: Error Recovery Enable bit 1 = MCP2502X/5X will recover into Listen-only mode from bus off 0 = MCP2502X/5X will recover into Normal mode from bus-off bit 5 TXONEN: Transmit on Erro
MCP2502X/5X NOTES: DS21664D-page 36 © 2007 Microchip Technology Inc.
MCP2502X/5X 6.0 PWM MODULE 6.1 Description reconfigure to their default conditions. This includes the PWM module itself being disabled and the GPIO being forced low, high or tri-state. There are two Pulse Width Modulation (PWM) modules (PWM1 and PWM2) that generate up to a 10-bit resolution output signal on GP2 and GP3, respectively. Each of these outputs can be separately enabled, with each having its own associated timer, duty cycle and period registers for controlling the PWM output shape.
MCP2502X/5X 6.3.2 PWM DUTY CYCLE When the PWMnDBH and 2-bit latch match TMRn concatenated with an internal 2-bit Q clock or 2 bits of the TMRn prescaler, the PWM output pin is cleared. The PWM duty cycle is specified by writing to the PWMnDCH and TnCON registers. Up to 10-bit resolution is available. The PWMnDCH contains the eight MSb’s, while the TnCON register contains the two LSb’s. This 10-bit value is represented by PWM1DCH:T1CON<1:0> for PWM Module 1 and PWM2DCH:T2CON<1:0> for PWM Module 2.
MCP2502X/5X REGISTER 6-3: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 TMR1ON — R/W-0 R/W-0 T1CKPS1 T1CKPS0 U-0 U-0 R/W-x R/W-x — — DC1B1 DC1B0 bit 7 bit 0 bit 7 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Disables Timer1 bit 6 Unimplemented: Read as '0' bit 5-4 T1CKPS1:T1CKPS0: Timer1 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 3-2 Unimplemented: Read as '0' bit 1-0 DC1B1:DC1B0: Least Significant PWM1 Duty Cycle bits Legend: REGISTER
MCP2502X/5X REGISTER 6-5: PR1: PERIOD REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PR1B7 PR1B6 PR1B5 PR1B4 PR1B3 PR1B2 PR1B1 PR1B0 bit 7 bit 7-0 bit 0 PR1B7:PR1B0: PWM1 Period Register bits Legend: REGISTER 6-6: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown PR2: PERIOD REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PR2B7 PR2B6 PR2B5 PR2B4 PR2B3 PR2
MCP2502X/5X 7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE 7.1 Description The Analog-to-Digital (A/D) module is a four-channel, 10-bit successive approximation type of A/D. The A/D allows conversion of an analog input signal to a corresponding 10-bit number. The four channels are multiplexed on the GP[3:0] pins. The converter is turned off/on via the ADCON0 register and each channel is individually enabled via the ADCON1 control register.
MCP2502X/5X 7.3.2 CONVERSION-ON-REQUEST MODE 7.4 If the Conversion-on-request mode is selected, the device performs an A/D conversion only after receiving a Read A/D Registers or Read Register Receive message (IRM). In the case of the Read A/D Registers command, all of the GPIO pins that have been configured as analog input channels will have an A/D conversion done before the data frame is sent.
MCP2502X/5X REGISTER 7-3: A/D MODULE COMPARE REGISTER MSB (ADCMPNH) R/W-x R/W-x R/W-x R/W-x ANnCMP9 ANnCMP8 ANnCMP7 ANnCMP6 R/W-x R/W-x ANnCMP5 R/W-x R/W-x ANnCMP4 ANnCMP3 ANnCMP2 bit 7 bit 7-0 bit 0 ANnCMP9:ANnCMP2: Most Significant A/D Compare bits Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared REGISTER 7-4: x = Bit is unknown A/D MODULE COMPARE REGISTER LSB (ADCMPNL) R/W-x R/W-x ANnCMP1 ANnCMP
MCP2502X/5X REGISTER 7-6: ADCON1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = Reserved bit 5-4 VCFG1:VCFG0: Voltage Reference Configuration bits bit 3-0 VCFG1:VCFG0 A/D VREF+ A/D VREF- 00 VDD VSS 01 External VREF+ VSS 10 VDD External VREF- 11 External VREF+ External VREF- PCFG3:PCFG0: A/D Port Configuration Co
MCP2502X/5X 7.5 Read A/D Registers Output Message When the MCP2502X/5X responds to a Read A/D Regs IRM with an OM, the analog values are contained in Register 7-7, Register 7-8 and Register 7-9.
MCP2502X/5X REGISTER 7-9: A/D OM RESULT REGISTER (AN10L) R-x R-x U-x U-x R-x R-x U-x U-x AN1R.1 AN1R.0 — — AN0R.1 AN0R.0 — — bit 7 bit 0 bit 7-6 AN1R.1:AN1R.0: A/D Channel 1, bits 1:0 results bit 5-4 Unimplemented: Reads as ‘0’ bit 3-2 AN0R.1:AN0R.
MCP2502X/5X 8.0 SPECIAL FEATURES OF THE MCP2502X/5X 8.1 Description There are a number of special circuits in the MCP2502X/5X that deal with the needs of real-time applications. These features are intended to maximize system reliability, minimize cost through elimination of external components and provide power-saving operating modes.
MCP2502X/5X REGISTER 8-1: CONFIGURATION REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — R R R R bit 13 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W R/W R/W R R R R R RSTEN FOSC1 FOSC0 bit 7 bit 0 bit 13-11 Unimplemented: Read as '0' bit 10-3 Reserved: do not attempt to modify bit 2 RSTEN: Enable RST input on GP7 1 = RST input Enabled 0 = RST input Disabled bit 1-0 FOSC1:FOSC0: Oscillator Selection bits 11 = HS oscillator 10 = Reserved for Test (EC oscillator) 01 = XT oscillat
MCP2502X/5X FIGURE 8-3: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RST VDD Rise Detect Power-on Reset S VDD OST Q Chip Reset 10-bit Ripple Counter OSC1 On-chip RC OSC PWRT 10-bit Ripple Counter Enable PWRT Enable OST 8.4.2 POWER-UP TIMER The Power-up Timer (PWRT) provides a fixed, 72 ms nominal time-out, on power-up only, from the POR. The Power-up Timer operates on an internal RC oscillator, with the device being kept in reset as long as the PWRT is active.
MCP2502X/5X 8.7 In-Circuit Serial Programming The MCP2502X/5X can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the device just before shipping the product, also allowing the most recent firmware (or a custom firmware) to be programmed.
MCP2502X/5X 9.0 ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings† Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature ...............................................................................................................................-65°C to +150°C Voltage on any pin with respect to Vss (except VDD and RST).......................................................
MCP2502X/5X 9.2 DC Characteristics Industrial (I): TAMB = -40°C to +85°C VCC = 2.7V to 5.5V Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V DC Characteristics Param. No. Sym VDD Characteristics Supply Voltage SVDD VDD Rise Rate to ensure internal power-on reset signal Min Max Units Test Conditions 2.7 4.5 5.5 5.5 V V XT and LP OSC configuration HS OSC configuration (Note 2) 0.05 — V/ms (Note 3) High-level input voltage VIH GPIO pins 2 VDD+0.
MCP2502X/5X 9.3 AC Characteristics Industrial (I): TAMB = -40°C to +85°C VCC = 2.7V to 5.5V Automotive (E): TAMB = -40°C to +125°C VCC = 4.5V to 5.5V AC Characteristics Param. No.
MCP2502X/5X FIGURE 9-2: I/O TIMING OSC1 I/O Pin (input) I/O Pin (output) New Value Old Value 10 20, 21 13 12 Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins. FIGURE 9-3: RESET, OST AND POWER-UP-TIMER VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Time-out Internal RESET 34 34 I/O Pins DS21664D-page 54 © 2007 Microchip Technology Inc.
MCP2502X/5X 9.4 A/D Converter Characteristics AC Converter Characteristics Param. No. Sym Min Max A/D resolution — 10-bits NINT A/D Integral error — less than ±1 LSb VREF+ = VDD = 5.12V, VSS- = VSS = 0 V (I TEMP) NDIF A/D Differential error — less than ±1 LSb VREF+ = VDD = 5.12V, VSS- = VSS = 0 V (I TEMP) NG A/D Gain error — less than ±1 LSb VREF+ = VDD = 5.12V, VSS- = VSS = 0 V NOFF A/D Offset error — less than ±2 LSb VREF+ = VDD = 5.
MCP2502X/5X NOTES: DS21664D-page 56 © 2007 Microchip Technology Inc.
MCP2502X/5X 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (208 mil) Example: MCP25050 e3 XXXXXXXXXXXXXX 0725NNN Example: XXXXXXXXXXX XXXXXXXXXXX MCP25055 XXXXXXXXXXX YYWWNNN 0737NNN Legend: XX...
MCP2502X/5X 14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 14 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .
MCP2502X/5X 14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 e h b A A2 c φ L A1 β L1 Units Dimension Limits Number of Pins α h MILLMETERS MIN N NOM MAX 14 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.
MCP2502X/5X NOTES: DS21664D-page 60 © 2007 Microchip Technology Inc.
MCP2502X/5X PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
MCP2502X/5X NOTES: DS21664D-page 62 © 2007 Microchip Technology Inc.
MCP2502X/5X APPENDIX A: REVISION HISTORY Revision D (January 2007) This revision includes updates to the packaging diagrams. © 2007 Microchip Technology Inc.
NOTES: DS21664D-page 64 © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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