Datasheet

MCP2502X/5X
DS21664D-page 38 © 2007 Microchip Technology Inc.
6.3.2 PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
PWMnDCH and TnCON registers. Up to 10-bit
resolution is available. The PWMnDCH contains the
eight MSb’s, while the TnCON register contains the two
LSb’s. This 10-bit value is represented by
PWM1DCH:T1CON<1:0> for PWM Module 1 and
PWM2DCH:T2CON<1:0> for PWM Module 2.
The following equation is used to calculate the PMW
duty cycle:
PWMnDCH can be written to at any time, but the duty
cycle value is not latched into PWMnDBH until after a
match between PRn and TMRn occurs (i.e., the period
is complete).
The PWMnDBH register and 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the PWMnDBH and 2-bit latch match TMRn
concatenated with an internal 2-bit Q clock or 2 bits of
the TMRn prescaler, the PWM output pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency is equal to:
In order to achieve higher resolution, the PWM
frequency must be decreased. In order to achieve
higher PWM frequency, the resolution must be
decreased. Table 6-1 lists example PWM frequencies
and resolutions for F
OSC = 20 MHz. TMRn prescaler
and PRn values are also shown.
TABLE 6-1: PWM FREQUENCIES AND RESOLUTIONS AT 20 MHZ
REGISTER 6-1: PWM1 DUTY CYCLE REGISTER MSB (PWM1DCH)
REGISTER 6-2: PWM2 DUTY CYCLE REGISTER MSB (PWM2DCH)
PWMDC PWMnDC()=*T
OSC
*TMRn (prescale)
Note: If the PWM duty cycle value is longer than
the PWM period (PWM duty cycle
= 100%), the PWM output pin will not be
cleared.
log F
OSC
()Fpwm()⁄()log 2()bits()⁄
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.30 kHz 208.30 kHz
Timer Prescaler (1, 4, 16) 1641111
PRn Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 5.5
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DC1B9 DC1B8 DC1B7 DC1B6 DC1B5 DC1B4 DC1B3 DC1B2
bit 7 bit 0
bit 7-0 DC1B9:DC1B2: Most Significant PWM0 Duty Cycle bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
DC2B9 DC2B8 DC2B7 DC2B6 DC2B5 DC2B4 DC2B3 DC2B2
bit 7 bit 0
bit 7-0 DC2B9:DC2B2: Most Significant PWM2 Duty Cycle bits
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown