Datasheet

MCP2502X/5X
DS21664D-page 20 © 2007 Microchip Technology Inc.
0Eh ADCON0
4
A/D Control Register; contains enable,
conversion rate, channel select bits
29h TXID2SIDL Transmit Buffer 2, Standard ID LSB,
Extended ID USB, and Extended ID
enable
0Fh ADCON1
4
A/D Control Register; contains voltage
reference source, conversion rate and
A/D input enable bits
2Ah TXID2EID8 Transmit Buffer 2, Extended ID MSB
10h STCON Scheduled Transmission Control Register 2Bh TXID2EID0 Transmit Buffer 2, Extended ID LSB
11h OPTREG2 Configuration options, including Sleep
mode, RTR message and error recovery
enables
2Ch ADCMP3H
4
Analog Channel 3 Compare Value
MSB
12h — Reserved 2Dh ADCMP3L
4
Analog Channel 3 Compare Value
LSb’s
13h — Reserved 2Eh ADCMP2H
4
Analog Channel 2 Compare Value
MSB
14h RXMSIDH Acceptance Filter Mask, Standard ID MSB 2Fh ADCMP2L
4
Analog Channel 2 Compare Value
LSb’s
15h RXMSIDL Acceptance Filter Mask, Standard ID LSB
and Extended ID USB
30h ADCMP1H
4
Analog Channel 1 Compare Value
MSB
16h RXMEID8 Acceptance Filter Mask, Extended ID
MSB
31h ADCMP1L
4
Analog Channel 1 Compare Value
LSb’s
17h RXMEID0 Acceptance Filter Mask, Extended ID LSB 32h ADCMP0H
4
Analog Channel 0 Compare Value
MSB
18h RXF0SIDH Acceptance Filter 0, Standard ID MSB 33h ADCMP0L
4
Analog Channel 0 Compare Value
LSb’s
19h RXF0SIDL Acceptance Filter 0, Standard ID LSB,
Extended ID USB, and Extended ID
enable
34h GPDDR
1
General Purpose I/O Data Direction
Register
1Ah RXF0EID8 Acceptance Filter 0, Extended ID MSB 35-44h USER[0:F]
2
User Defined Bytes (0-15)
TABLE 3-1: USER MEMORY MAP (CONTINUED)
Address Name Description Address Name Description
Note 1: GPDDR is mapped to 1Fh is SRAM and not offset by 1Ch.
2: User memory (35h-44h) is not transferred to RAM on power-up and can only be accessed via “Read User Mem”
commands.
3: Cannot be modified from initial programmed values.
4: Unimplemented on MCP2502X devices and read 0x00 (exception, ADCON1 = 0x0F).
TABLE 3-2: ACCESSIBLE RAM REGISTERS NOT IN THE EPROM MAP
Addr* Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Value on
POR
Value on
RST
1Fh** GPDDR — DDR6 DDR4 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111
18h EFLG ESCF RBO TXEP TXEP RXEP TXWAR RXWAR EWARN 0000 0000 0000 0000
19h TEC Transmit Error Counters 0000 0000 0000 0000
1Ah REC Receive Error Counters 0000 0000 0000 0000
50h ADRES3H AN3.9 AN3.8 AN3.6 AN3.6 AN3.5 AN3.4 AN3.3 AN3.2 xxxx xxxx uuuu uuuu
51h ADRES3L AN3.1 AN3.0
— — — — — — xx-- ---- uu-- ----
52h ADRES2H AN2.9 AN2.8 AN2.6 AN2.6 AN2.5 AN2.4 AN2.3 AN2.2 xxxx xxxx uuuu uuuu
53h ADRES2L AN2.1 AN2.0
— — — — — — xx-- ---- uu-- ----
54h ADRES1H AN1.9 AN1.8 AN1.6 AN1.6 AN1.5 AN1.4 AN1.3 AN1.2 xxxx xxxx uuuu uuuu
55h ADRES1L AN1.1 AN1.0
— — — — — — xx-- ---- uu-- ----
56h ADRES0H AN0.9 AN0.8 AN0.6 AN0.6 AN0.5 AN0.4 AN0.3 AN0.2 xxxx xxxx uuuu uuuu
57h ADRES0L AN0.1 AN0.0
— — — — — — xx-- ---- uu-- ----
* These addresses are used when using the “Write Register” or “Read Register” command
** The GPDDR register is not offset to RAM the same as the other registers in the EPROM