Datasheet

MCP2502X/5X

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH GPIO MODULE

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAEN ERREN TXONEN SLPEN MTYPE PDEFEN PUSLP PUNRM

bit 7 bit 0

bit 7 CAEN: Command Acknowledge Enable bit

1 = Enables the command acknowledge message (TXID1)

0 = Enables the receive overflow message (TXID1)

bit 6 ERREN: Error Recovery Enable bit

1 = MCP2502X/5X will recover into Listen-only mode from bus off

0 = MCP2502X/5X will recover into Normal mode from bus-off

bit 5 TXONEN: Transmit on Error Condition bit(REC or TEC)

1 = Enable, will send message if error counter(s) go high enough

0 = Disable, will NOT send message regardless of error counter values

bit 4 SLPEN: Low power SLEEP mode enable/disable

1 = Device will enter Sleep if bus is idle for at least 1408 bit times

0 = SLEEP mode is disabled

bit 3 MTYPE: Determines if information request messages use RTR or not

1 = RTR is NOT used for IRM (Data Frame)

0 = RTR is used for IRM (Remote Frame)

bit 2 PDEFEN: Enables PWM outputs to return to POR default values when CAN bus communication

is lost

1 = Enables PWM output default values

0 = Disables PWM output default values

bit 1 PUSLP: Allows device to enter SLEEP while in Listen-only mode during power-up sequence

1 = Enables SLEEP when in Listen-only mode during power-up sequence

0 = Disables SLEEP when in Listen-only mode during power-up sequence

bit 0 PUNRM: Enters Normal mode after completing self-configuration during power-up sequence

1 = Enters “Normal” mode after completing self-configuration during power-up sequence

0 = Enables “Listen-only” mode after completing self-configuration during power-up sequence

and waits for an error-free message before switching to Normal mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Addr Name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Value on

POR

Value on

RST

Bank 0

34h GPDDR

— DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 -111 1111 -111 1111

00h IOINTEN GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC 0000 0000 0000 0000

01h IOINTPO GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL 0000 0000 0000 0000

04h OPTREG1 GPPU

CLKEN CLKPS1 CLKPS0 — CMREQ AQT1 AQT0 0000 ---- 0000 ----

Legend: x = unknown, U = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used by module.