Datasheet

© 2007 Microchip Technology Inc. DS20090C-page 7
MCP23016
1.7.2 OUTPUT LATCH REGISTERS
Two registers provide access to the two port output
latches:
• OLAT0 (provides access to the output latch for
port GP0)
• OLAT1 (provides access to the output latch for
port GP1)
A read from these registers results in a read of the latch
that controls the output and not the actual port. A write
to these registers updates the output latch that controls
the output.
REGISTER 1-3: OLAT0 - OUTPUT LATCH REGISTER 0
REGISTER 1-4: OLAT1 - OUTPUT LATCH REGISTER 1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL0.7 OL0.6 OL0.5 OL0.4 OL0.3 OL0.2 OL0.1 OL0.0
bit 7 bit 0
bit 7-0 OL0.0:O0.7: Reflects the logic level on the output latch.
1 = Logic ‘1’
0 = Logic ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL1.7 OL1.6 OL1.5 OL1.4 OL1.3 OL1.2 OL1.1 OL1.0
bit 7 bit 0
bit 7-0 OL1.0:O1.7: Reflects the logic level on the output latch.
1 = Logic ‘1’
0 = Logic ‘0’
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown