Datasheet
Table Of Contents
- Features
- CMOS Technology
- Packages
- Package Types
- Block Diagram
- 1.0 Device OvervieW
- 1.1 Pin Descriptions
- 1.2 Power-on Reset (POR)
- 1.3 Power-up Timer (PWRT)
- 1.4 Clock Generator
- 1.5 I2C Bus Interface/ Protocol Handler
- 1.6 Address Decoder
- 1.7 Register Block
- 1.8 Serializer/Deserializer
- 1.9 Interrupt Logic
- 2.0 Electrical Characteristics
- 2.1 DC Characteristics
- TABLE 2-1: DC Characteristics
- FIGURE 2-1: respOnse time
- TABLE 2-2: response time
- FIGURE 2-2: TEST POINT Clock Timing
- TABLE 2-3: TEST POINT Clock Timing
- TABLE 2-4: Power-up Timer Requirements
- FIGURE 2-3: I2C Bus Start/Stop Bits Timing
- FIGURE 2-4: I2C Bus Data Timing
- TABLE 2-5: I2C Bus Data Requirements
- FIGURE 2-5: GP0 and GP1 POrt Timings
- 2.1 DC Characteristics
- 3.0 Package InFormation
- Appendix A: Revision History
- Product Identification System
- Worldwide Sales and Service
© 2007 Microchip Technology Inc. DS20090C-page 3
MCP23016
1.0 DEVICE OVERVIEW
The MCP23016 device provides 16-bit, general
purpose, parallel I/O expansion for I
2
C bus
applications.
This device includes high-current drive capability, low
supply current and individual I/O configuration. I/O
expanders provide a simple solution when additional
I/Os are needed for ACPI, power switches, sensors,
push buttons, LEDs and so on.
The MCP23016 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
input or output register. The polarity of the read register
can be inverted with the polarity inversion register (see
Section 1.7.3, “Input Polarity Registers”). All
registers can be read by the system master.
The open-drain interrupt output is activated when any
input state differs from its corresponding input port
register state. This is used to indicate to the system
master that an input state has changed. The interrupt
capture register captures port value at this time. The
Power-on Reset sets the registers to their default val-
ues and initializes the device state machine.
Three device inputs (A0 - A2) determine the I
2
C
address and allow up to eight I/O expander devices to
share the same I
2
C bus.
1.1 Pin Descriptions
TABLE 1-1: PINOUT DESCRIPTION
Pin Name
PDIP,
SOIC,
SSOP
Pin No.
QFN
Pin No.
I/O/P
Type
Buffer
Type
Description
CLK 9 6 I ST Clock source input
TP 10 7 O — Test Pin (This pin must be left floating)
GP1.0 2 27 I/O TTL D0 digital input/output for GP1
GP1.1 3 28 I/O TTL D1 digital input/output for GP1
GP1.2 4 1 I/O TTL D2 digital input/output for GP1
GP1.3 5 2 I/O TTL D3 digital input/output for GP1
GP1.4 7 4 I/O TTL D4 digital input/output for GP1
GP1.5 11 8 I/O ST D5 digital input/output for GP1
GP1.6 12 9 I/O ST D6 digital input/output for GP1
GP1.7 13 10 I/O ST D7 digital input/output for GP1
GP0.0 21 18 I/O TTL D0 digital input/output for GP0
GP0.1 22 19 I/O TTL D1 digital input/output for GP0
GP0.2 23 20 I/O TTL D2 digital input/output for GP0
GP0.3 24 21 I/O TTL D3 digital input/output for GP0
GP0.4 25 22 I/O TTL D4 digital input/output for GP0
GP0.5 26 23 I/O TTL D5 digital input/output for GP0
GP0.6 27 24 I/O TTL D6 digital input/output for GP0
GP0.7 28 25 I/O TTL D7 digital input/output for GP0
SCL 14 11 I ST Serial clock input
SDA 15 12 I/O ST Serial data I/O
INT
6 3 O OD Interrupt output
A0 16 13 I ST Address input 1
A1 17 14 I ST Address input 2
A2 18 15 I ST Address input 3
V
SS 1, 8, 19 5, 16, 26 P — Ground reference for logic and I/O pins
V
DD 20 17 P — Positive supply for logic and I/O pins