Datasheet
Table Of Contents
- Features
- CMOS Technology
- Packages
- Package Types
- Block Diagram
- 1.0 Device OvervieW
- 1.1 Pin Descriptions
- 1.2 Power-on Reset (POR)
- 1.3 Power-up Timer (PWRT)
- 1.4 Clock Generator
- 1.5 I2C Bus Interface/ Protocol Handler
- 1.6 Address Decoder
- 1.7 Register Block
- 1.8 Serializer/Deserializer
- 1.9 Interrupt Logic
- 2.0 Electrical Characteristics
- 2.1 DC Characteristics
- TABLE 2-1: DC Characteristics
- FIGURE 2-1: respOnse time
- TABLE 2-2: response time
- FIGURE 2-2: TEST POINT Clock Timing
- TABLE 2-3: TEST POINT Clock Timing
- TABLE 2-4: Power-up Timer Requirements
- FIGURE 2-3: I2C Bus Start/Stop Bits Timing
- FIGURE 2-4: I2C Bus Data Timing
- TABLE 2-5: I2C Bus Data Requirements
- FIGURE 2-5: GP0 and GP1 POrt Timings
- 2.1 DC Characteristics
- 3.0 Package InFormation
- Appendix A: Revision History
- Product Identification System
- Worldwide Sales and Service
MCP23016
DS20090C-page 24 © 2007 Microchip Technology Inc.
TABLE 2-5: I
2
C BUS DATA REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
100 THIGH Clock High Time 100 kHz mode 4.0 — µs (Note 1)
400 kHz mode 0.6 — µs
101 T
LOW Clock Low Time 100 kHz mode 4.7 — µs (Note 1)
400 kHz mode 1.3 — µs
102 T
R SDA and SCL Rise
Time
100 kHz mode — 1000 ns (Note 1)
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 - 400 pF
103 T
F SDA and SCL Fall
Time
100 kHz mode — 300 ns (Note 1)
400 kHz mode 20 + 0.1 CB 300 ns CB is specified to be from
10 - 400 pF
90 T
SU:STA START Condition
Setup Time
100 kHz mode 4.7 — µs Only relevant for repeated
START condition (Note 1)
400 kHz mode 0.6 — µs
91 THD:STA START Condition
Hold Time
100 kHz mode 4.0 — µs After this period, the first
clock pulse is generated
(Note 1)
400 kHz mode 0.6 — µs
106 THD:DAT Data Input Hold
Time
100 kHz mode 0 — ns (Note 1)
400 kHz mode 0 0.9 µs
107 T
SU:DAT Data Input Setup
Time
100 kHz mode 250 — ns (Note 1) (Note 3)
400 kHz mode 100 — ns
92 T
SU:STO STOP Condition
Setup Time
100 kHz mode 4.7 — µs (Note 1)
400 kHz mode 0.6 — µs
109 TAA Output Valid from
Clock
100 kHz mode — 3500 ns (Note 1) (Note 2)
400 kHz mode — — ns
110 T
BUF Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be free
before a new transmis-
sion can start (Note 1)
400 kHz mode 1.3 — µs
CB Bus Capacitive Loading — 400 pF
111 TWAIT Clock wait time
after ninth pulse
100 kHz mode 12 µs — µs Time the bus must remain
free after the ninth clock
pulse before a new
transmission can start.
400 kHz mode 12 µs — µs
Note 1: These parameters are characterized but not tested.
2: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: A Fast mode (400 kHz) I
2
C bus device can be used in a Standard mode (100 kHz) I
2
C bus system, but the
requirement T
SU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line T
R max.+TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I
2
C bus specification), before the SCL line is released.