Datasheet
Table Of Contents
- Features
- CMOS Technology
- Packages
- Package Types
- Block Diagram
- 1.0 Device OvervieW
- 1.1 Pin Descriptions
- 1.2 Power-on Reset (POR)
- 1.3 Power-up Timer (PWRT)
- 1.4 Clock Generator
- 1.5 I2C Bus Interface/ Protocol Handler
- 1.6 Address Decoder
- 1.7 Register Block
- 1.8 Serializer/Deserializer
- 1.9 Interrupt Logic
- 2.0 Electrical Characteristics
- 2.1 DC Characteristics
- TABLE 2-1: DC Characteristics
- FIGURE 2-1: respOnse time
- TABLE 2-2: response time
- FIGURE 2-2: TEST POINT Clock Timing
- TABLE 2-3: TEST POINT Clock Timing
- TABLE 2-4: Power-up Timer Requirements
- FIGURE 2-3: I2C Bus Start/Stop Bits Timing
- FIGURE 2-4: I2C Bus Data Timing
- TABLE 2-5: I2C Bus Data Requirements
- FIGURE 2-5: GP0 and GP1 POrt Timings
- 2.1 DC Characteristics
- 3.0 Package InFormation
- Appendix A: Revision History
- Product Identification System
- Worldwide Sales and Service
MCP23016
DS20090C-page 22 © 2007 Microchip Technology Inc.
FIGURE 2-3: I
2
C BUS START/STOP BITS TIMING
TABLE 2-5: I
2
C BUS START/STOP BITS REQUIREMENTS
Param
No.
Symbol Characteristic Min
Ty
p
Max Units Conditions
90 T
SU:STA START condition 100 kHz mode 4700 — — ns Only relevant for Repeated
START condition (Note 1)
Setup time 400 kHz mode 600 — —
91 THD:STA START condition 100 kHz mode 4000 — — ns After this period, the first
clock pulse is generated
(Note 1)
Hold time 400 kHz mode 600 — —
92 TSU:STO STOP condition 100 kHz mode 4700 — — ns
Setup time 400 kHz mode 600 — —
93 T
HD:STO STOP condition 100 kHz mode 4000 — — ns
Hold time 400 kHz mode 600 — —
Note 1: These parameters are characterized but not tested.
91
92
93
SCL
SDA
START
Condition
STOP
Condition
90