Datasheet

© 2007 Microchip Technology Inc. Preliminary DS21894C-page 21
MCP2122
4.3 Timing Diagrams and Specifications
FIGURE 4-3: EXTERNAL CLOCK TIMING
TABLE 4-3: EXTERNAL CLOCK TIMING REQUIREMENTS
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature: –40°C ≤ T
A ≤ +125°C (Extended)
Operating Voltage V
DD range is described in
Section 4.1 “DC Characteristics”
Param.
No.
Sym Characteristic Min Typ
(1)
Max Units Conditions
1T
XCLK External 16XCLK Period
(2, 3)
542.5 — — ns
1A F
XCLK External 16XCLK
Frequency
(2, 3)
DC — 1.8432 MHz
1C E
XCLK Clock Error
(4, 5)
— — ±2 % Note 5
3T
XCLKL,
TXCLKH
Clock in (16XCLK)
Low or High Time
50 — — ns
4T
XCLKR,
TXCLKF
Clock in (16XCLK)
Rise or Fall Time
(5)
— — 7.5 ns Note 5
Note 1: Data in the Typical (“Typ”) column is at 5V, +25°C, unless otherwise stated. These parameters are for
design guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: A duty cycle of no more than 60/40 (High-Time/Low-Time or Low-Time/High-Time) is recommended for
external clock inputs.
4: This is the clock error from the desired clock frequency. The total system clock error includes the error from
the transmitter and the error of receiver (from the desired clock frequency). If the transmitter is 2% fast from
the target frequency, and the receiver is 2% slow from the target frequency, the total error is 4%.
5: These parameters (shaded) are characterized but are not tested. These values should be used for design
guidance only.
16XCLK
Q4
Q1 Q2
Q3 Q4 Q1
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