MCP2021/2/1P/2P
DS22018F-page 30 © 2005-2012 Microchip Technology Inc.
FIGURE 2-6: Regulator BUS WAKE Timing Diagram.
FIGURE 2-7: RESET
Timing Diagram.
VOUT
LBUS
0.4VBB
TVEVR
VREG
TBDB + TBACTVE
RESET
VBB
6.0V
VREG
5.0V
5.0V
4.0V
3.5V
TRPU
TRPD
TRPD
TRPU
