Datasheet

© 2005-2012 Microchip Technology Inc. DS22018F-page 29
MCP2021/2/1P/2P
2.5 Timing Diagrams and Specifications
FIGURE 2-4: Bus Timing Diagram.
FIGURE 2-5: Regulator CS/LWAKE Timing Diagram.
.95VLBUS
.0.4VBB
TTRANSPDR
TRECPDR
TTRANSPDF
TRECPDF
TXD
L
BUS
RXD
Internal TXD/RXD
Compare
FAULT Sampling
T
FAULT
T
FAULT
FAULT/TXE Output
Stable
Stable
Stable
Match
Match
Match
Match
Match
Hold
Value
Hold
Value
50%
50%
.50VBB
50%
50%
0.0V
TCSPD
T
CSOR
CS/LWAKE
VOUT
VREG