Datasheet

MCP2003/4/3A/4A
DS20002230E-page 10  2010-2013 Microchip Technology Inc.
The WAKE pin has an internal 800K pull up to VBB. A
falling edge on the WAKE
pin causes the device to
wake from Power-Down mode. Upon waking, the
MCP2003/3A will enter Ready mode.
1.5.4 FAULT/TXE
This pin is only available on the MCP2004/2004A. This
pin is bidirectional and allows disabling of the
transmitter, as well as fault reporting related to
disabling the transmitter. This pin is an open-drain
output, with states as defined in TABLE 1-3: “FAULT/
TXE Truth Table”. The transmitter is disabled
whenever this pin is low (‘0’), either from an internal
Fault condition or by an external drive. While the
transmitter is disabled, the internal 30 k pull-up
resistor on the L
BUS pin is also disconnected to reduce
current.
TABLE 1-3: FAULT/TXE TRUTH TABLE
1.5.5 TRANSMIT DATA INPUT (T
XD)
The Transmit Data Input pin has an internal pull-up.
The LIN pin is low (dominant) when T
XD is low, and high
(recessive) when T
XD is high.
For extra bus security, T
XD is internally forced to ‘1’
whenever the transmitter is disabled regardless of
external T
XD voltage.
1.5.5.1 TXD Dominant Timeout
If TXD is driven low for longer than approximately
25 ms, the L
BUS pin is switched to recessive mode and
the part enters TOFF Mode. This is to prevent the LIN
node from permanently driving the LIN Bus dominant.
The transmitter is reenabled on T
XD rising edge.
1.5.6 GROUND (VSS)
This is the Ground pin.
1.5.7 LIN BUS (LBUS)
The bidirectional LIN Bus pin (LBUS) is controlled by the
T
XD input. LBUS has a current limited open collector
output. To reduce EMI, the edges during the signal
changes are slope controlled and include corner
rounding control for both falling and rising edges.
The internal LIN receiver observes the activities on the
LIN bus, and matches the output signal R
XD to follow
the state of the L
BUS pin.
1.5.7.1 Bus Dominant Timer
The Bus Dominant Timer is an internal timer that
deactivates the L
BUS transmitter after approximately
25 milliseconds of dominant state on the L
BUS pin. The
timer is reset on any recessive L
BUS state.
The LIN bus transmitter will be reenabled after a
recessive state on the L
BUS pin as long as CS is high.
Disabling can be caused by the LIN bus being
externally held dominant, or by T
XD being driven low.
Additionally, on the MCP2004/2004A, the FAULT
pin
will be driven low to indicate the Transmitter Off state.
1.5.8 BATTERY (VBB)
This is the Battery Positive Supply Voltage pin.
1.5.9 VOLTAGE REGULATOR ENABLE
OUTPUT (V
REN)
This is the External Voltage Regulator Enable pin.
Open source output is pulled high to V
BB in all modes,
except Power-Down.
Note: The FAULT/TXE pin is true (‘0’) whenever
the internal circuits have detected a short
or thermal excursion and have disabled
the L
BUS output driver.
TXD
In
RXD
Out
LINBUS
I/O
Thermal
Override
FAULT/
TXE
Definition
External
Input
Driven
Output
LHV
BB OFF H L FAULT, TXD driven low, LINBUS shorted to VBB
(Note 1)
HHV
BB OFF H H OK
L L GND OFF H H OK
H L GND OFF H H OK, data is being received from the LINBUS
xxVBB ON H L FAULT, Transceiver in thermal shutdown
xxV
BB x L x NO FAULT, the CPU is commanding the
transceiver to turn off the transmitter driver
Legend: x = don’t care.
Note 1: The FAULT/TXE is valid after approximately 25 µs after TXD falling edge. This is to eliminate false fault
reporting during bus propagation delays.